Semiconductor Field Plate Structure for On-Resistance and Gate Charge
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Solution Overview
Problem
Conventional LDMOS transistor devices face challenges in enhancing electrical performance and reducing power loss in high-voltage semiconductor units, particularly in terms of on-resistance and gate charge, which affect their voltage endurance and efficiency.
Innovation Solution
The semiconductor device incorporates field plates electrically connected to the gate and source regions, allowing for adjustments in on-resistance and gate charge, thereby improving electrical performance and reducing power loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional LDMOS transistor structure is used, then device can achieve high breakdown voltage, but on-resistance and power loss cannot be sufficiently reduced
Solution Approach 1:
The device is segmented into multiple independent units, each comprising a gate structure, source region, drain region, and field plates. This segmentation allows each unit to be optimized independently for low on-resistance while maintaining high breakdown voltage, thereby reducing overall power loss without proportionally increasing complexity
Solution Approach 2:
The field plates are nested between the gate structure and the drain region, with each field plate positioned to overlap partially with the gate structure. This nested configuration enables the field plates to modulate the electric field and reduce on-resistance while being integrated within the existing device structure, minimizing additional complexity
2Loss of energy
If drift region area is increased to reduce on-resistance, then power loss decreases, but device area and complexity increase
Solution Approach 1:
Instead of increasing the drift region area in the planar dimension, the invention introduces field plates in the vertical dimension above the gate structure. These field plates modulate the electric field distribution vertically, enabling reduced on-resistance and power loss without proportionally increasing the device footprint
3Reliability
If field plates are electrically connected to gate structure, then on-resistance is reduced, but gate charge increases
Solution Approach 1:
The field plates are positioned locally between the gate structure and drain region, with specific portions overlapping the gate structure. This localized configuration allows the electric field to be modulated precisely where needed to reduce on-resistance, while the limited overlap area constrains the additional gate charge to acceptable levels
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The connection of field plates to the gate and source regions enhances the semiconductor device's electrical performance and reduces power loss, meeting specific product requirements by optimizing on-resistance and gate charge characteristics.
Implementation Method 1
The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.