Semiconductor Device With Field Plates For Breakdown Voltage
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Solution Overview
Problem
The FLR structure used to increase breakdown voltage in semiconductor devices results in an increased footprint, making it difficult to reduce the size of the device while maintaining high voltage sustainability.
Innovation Solution
A semiconductor device with a RESURF layer and field plates, where the RESURF layer is positioned between impurity regions and field plates are used to generate capacitive couplings that distribute electric field uniformly, reducing the need for ring-shaped P-type impurity regions and thus minimizing the device's footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FLR structure is used to increase breakdown voltage, then breakdown voltage is improved, but device footprint increases
Solution Approach 1:
The invention changes the electrical parameters by introducing field plates with specific capacitance values (first field plate with capacitance C1, second field plate with capacitance C2 where C1≠C2) to redistribute the electric field. This parameter change allows achieving the required breakdown voltage without expanding the device footprint, as the capacitive coupling selectively modifies the electric field distribution rather than relying on extended physical structures like FLR rings.
Solution Approach 2:
The field plates act as intermediary elements between the P-type impurity regions, providing capacitive coupling to redistribute the electric field. These intermediary structures (field plates with different capacitances) mediate the electric field distribution, allowing the device to achieve high breakdown voltage without requiring the large-area FLR structure, thus resolving the contradiction between reliability and footprint.
2Stress or pressure
If N-type impurity regions of low concentration are used in FLR structure, then electric field is reduced, but peripheral area increases
Solution Approach 1:
Field plates are introduced as intermediary elements that provide capacitive coupling between P-type impurity regions. The first field plate (capacitance C1) and second field plate (capacitance C2) with different capacitance values act as mediators to redistribute the electric field, reducing the need for low-concentration N-type impurity regions that would otherwise occupy large peripheral areas in traditional FLR structures.
Solution Approach 2:
The invention changes the electric field distribution by introducing capacitive coupling parameters (C1 and C2) rather than relying on impurity concentration gradients. By adjusting the capacitance values of the field plates, the electric field can be reduced in the peripheral regions without requiring extensive low-concentration N-type impurity regions, thus reducing the peripheral area while maintaining electric field control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for a reduced footprint while maintaining a predetermined breakdown voltage by distributing electric field uniformly across the device, preventing electric field concentration and avalanche breakdown.
Implementation Method 1
The plurality of field plates includes a lower field plate and an upper field plate. The lower field plate is capable of generating a lower capacitive coupling with the substrate. The upper field plate is located at a position farther from the substrate than the lower field plate, and capable of generating an upper capacitive coupling with the lower field plate.
Data Source
AI summary
A semiconductor includes an N-type impurity region provided in a substrate. A P-type RESURF layer is provided at a top face of the substrate in the N-type impurity region. A P-well has an impurity concentration higher than that of the P-type RESURF layer, and makes contact with the P-type RESURF layer at the top face of the substrate in the N-type impurity region. A first high-voltage-side plate is electrically connected to the N-type impurity region, and a low-voltage-side plate is electrically connected to a P-type impurity region. A lower field plate is capable of generating a lower capacitive coupling with the substrate. An upper field plate is located at a position farther from the substrate than the lower field plate, and is capable of generating an upper capacitive coupling with the lower field plate whose capacitance is greater than the capacitance of the lower capacitive coupling.