Semiconductor Field-Stop Layer Dopant Selection for Thermal Runaway
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Solution Overview
Problem
Existing semiconductor devices face challenges in balancing resistance to element destruction during short circuits with suppressing thermal runaway and reducing on-state voltage variation, with high hole injection efficiency leading to increased leakage current and thermal runaway risks.
Innovation Solution
A semiconductor device with a field-stop layer having a higher impurity concentration than the drift layer, a buffer layer with a peak impurity concentration lower than the collector layer, and using selenium or sulfur as dopants for the field-stop layer to reduce impurity concentration gradient and prevent thermal runaway, while phosphorus is used for the buffer layer to suppress hole implantation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a field-stop layer with high impurity concentration is formed using phosphorus, then voltage resistance is improved, but thermal runaway occurs due to excessive hole injection
Solution Approach 1:
The patent changes the dopant material parameter from phosphorus to selenium or sulfur for the field-stop layer. This parameter change reduces the hole injection efficiency while maintaining the impurity concentration gradient, thereby preventing thermal runaway while preserving voltage resistance. The specific patent text states: 'by forming an n-type FS layer 14, which is deep in the depth direction from the Si substrate back surface and which has a concentration gradient such that the impurity concentration becomes gradually lower from the p +[0033]Furthermore, by providing an n +[0038]The impurity concentration and thickness (or diffusion depth) of each layer described thus far can be obtained by measuring the spread resistance using, for example, a heretofore known spread resistance measuring instrument, and converting from the spread resistance value.
2Reliability
If the Si substrate is thinned to reduce on-state voltage, then on-state voltage is reduced, but the wafer is liable to crack during manufacturing
Solution Approach 1:
The patent performs back surface thinning and field-stop layer formation before front surface processing. This preliminary action on the back surface allows controlled thickness reduction without compromising the mechanical strength needed for subsequent front surface trench formation and other manufacturing steps. The patent text states: 'A back grinding process whereby the wafer is thinned from the back surface by grinding, etching, or the like, has been proposed as a process for thinning the wafer (for example, refer to PTL 1).'
3Reliability
If a two-stage buffer layer is formed to improve voltage resistance, then breakdown voltage is improved, but manufacturing complexity increases
Solution Approach 1:
The patent uses selenium or sulfur dopants that naturally form a suitable concentration gradient in the field-stop layer through diffusion, eliminating the need for a complex two-stage buffer layer structure. This parameter change in dopant material achieves the desired electrical characteristics with a simpler overall layer structure. The patent text indicates that selenium or sulfur have higher diffusion constants than phosphorus, enabling efficient formation of the required impurity concentration distribution.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively balances resistance to element destruction during short circuits by spreading the space-charge region early and suppressing thermal runaway, while reducing on-state voltage variation and preventing avalanche breakdown.
Implementation Method 1
a method whereby the FS-layer is efficiently formed as a deep diffusion layer with a low impurity concentration using an n-type impurity such as selenium (Se) or sulfur (S), which have a higher diffusion constant than that of phosphorus
Implementation Method 2
a two-stage buffer layer (FS layer), configured of a diffusion layer with a low impurity concentration formed deeply from the wafer back surface side and a diffusion layer with a high impurity concentration formed shallowly from the wafer back surface side, is formed using phosphorus (P) as the dopant
Data Source
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AI summary
An n-type FS layer (14) has a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type FS layer (14) together with the total impurity of an n- type drift layer (1). Also, the n-type FS layer (14) has a concentration gradient such that the impurity concentration of the n-type FS layer (14) decreases from a p+ type collector layer (15) toward a p-type base layer (5), and the diffusion depth is 20µm or more. Furthermore, an n+ type buffer layer (13) of which the peak impurity concentration is higher than that of the n-type FS layer (14) at 6 × 1015cm-3 or more, and one-tenth or less of the peak impurity concentration of the p+ type collector layer (15), is included between the n-type FS layer (14) and p+ type collector layer (15). Because of this, it is possible to provide a field-stop (FS) insulated gate bipolar transistor such as to balance an improvement in resistance to element destruction when a short circuit occurs with suppressing thermal runaway destruction, and furthermore, to reduce variation in on-state voltage.