Semiconductor Pattern Etching with Filling Masks for OPC Variation
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Solution Overview
Problem
In semiconductor manufacturing, the optical proximity effect leads to line width variations and poor formation quality when transferring patterns from a mask layout to a wafer, especially in regions with densely and isolated patterns, resulting in defects and reduced electrical performance.
Innovation Solution
A method is developed to form a semiconductor structure by creating discrete mask layers and a filling layer between them, using the mask layers and filling layer as masks to etch the pattern definition layer, optimizing pattern density and contrast to improve line width and edge roughness, thereby enhancing electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the same mask layout is used for both isolated pattern regions and dense pattern regions, then the manufacturing process is simple, but line width variations occur due to optical proximity effects
Solution Approach 1:
The patent applies local quality by creating different mask layouts for isolated pattern regions and dense pattern regions. The isolated pattern region uses a first mask layout while the dense pattern region uses a second mask layout with different pattern densities, allowing each region to be optimized for its specific characteristics and reducing line width variations caused by optical proximity effects.
2Manufacturing precision
If bars are added between patterns to optimize local pattern density, then pattern formation quality improves, but device complexity increases
Solution Approach 1:
The patent segments the chip into isolated pattern regions and dense pattern regions, and further segments the mask layout into a first mask layout for isolated patterns and a second mask layout for dense patterns. This segmentation allows independent optimization of each region's pattern density without unnecessarily complicating the entire mask layout.
3Manufacturing precision
If pattern density is increased to improve contrast, then line edge roughness decreases, but optical interference effects increase
Solution Approach 1:
The patent optimizes pattern density locally for each region type. The dense pattern region uses a second mask layout with higher pattern density to improve line edge roughness in that specific area, while the isolated pattern region uses a first mask layout with lower density to avoid optical interference. This localized optimization allows each region to achieve its best performance without causing harmful effects in other regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves the formation quality of semiconductor structures by reducing line width roughness and line edge roughness, leading to better electrical performance and manufacturing efficiency.
Implementation Method 1
the filling material layer is formed using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process
Implementation Method 2
the filling material layer is formed using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process
Implementation Method 3
the filling material layer at the bottom of the first openings and the filling material layer located at the top of the mask layers are removed using a blanket dry etching process
Data Source
AI summary
A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base, where the base includes first regions and a second region located between the first regions; forming a pattern definition layer on the base; forming discrete mask layers on the pattern definition layer, the mask layers and the base defining openings, where openings of the first regions serve as first openings, and an opening of the second region serves as a second opening; forming a filling layer in the second opening; and etching, using the mask layers and the filling layer as masks, the pattern definition layer exposed from the first openings, to form target patterns. In embodiments and implementations of this application, the filling layer is formed between the mask layers of the second region, to obtain a mask that finally etches the pattern definition layer, so that the formed target patterns meet process requirements, which is conducive to improving electrical performance of the semiconductor structure.