Semiconductor Isolation Structure Filling to Prevent Voids and Leakage
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Solution Overview
Problem
The shrinking size of semiconductor devices leads to increased capacitive coupling, leakage current, and short circuit issues due to voids or seams in the fill material, affecting the reliability and electrical performance of memory devices.
Innovation Solution
The method improves the control accuracy of the etch-back process by enhancing the uniformity of the planarization process and combining it with the implantation process to adjust the aspect ratio of openings and trenches, reducing the likelihood of voids or seams during the filling process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of memory devices is continuously shrunk to increase integration density, then the storage capacity is improved, but capacitive coupling between adjacent elements increases and leakage current problems worsen
Solution Approach 1:
The patent divides the filling process into multiple stages: first forming a fill material layer, then performing selective etching to remove portions of the fill material, and finally forming additional conductive layers. This segmentation allows precise control over the final structure geometry, enabling reduced capacitive coupling while maintaining high integration density.
Solution Approach 2:
The patent applies different properties to different regions of the structure by selectively etching specific areas of the fill material. The etching process creates regions with varying depths and geometries, allowing local optimization of electrical properties to reduce leakage current and capacitive coupling in specific areas while maintaining overall high density.
2Quantity of substance
If the size of memory devices is continuously shrunk, then the storage capacity is improved, but voids or seams are formed in the fill material during the filling process
Solution Approach 1:
The patent performs preliminary actions by first forming the fill material layer and then selectively etching portions before completing the filling process. This preliminary etching creates a modified geometry that facilitates subsequent filling, preventing void formation by ensuring proper material flow and contact between layers.
Solution Approach 2:
The patent introduces dimensional changes by performing selective etching at different depths and creating multi-level structures. This dimensional approach allows the fill material to be deposited in a controlled manner, ensuring complete coverage and eliminating voids or seams that would occur with simple planar filling.
3Measurement precision
If the planarization process is improved to enhance uniformity, then the control accuracy of etch-back depth is improved, but the process complexity increases
Solution Approach 1:
The patent introduces an intermediary step of selective etching before the final filling process. This intermediary process acts as a mediator that simplifies the overall complexity by creating a pre-conditioned structure, making the subsequent filling more uniform and reducing the need for complex planarization adjustments.
4Ease of manufacture
If the upper portion of the opening has a larger width to improve filling capability, then the filling process reliability is improved, but the aspect ratio control becomes more difficult
Solution Approach 1:
The patent applies dynamic geometry by creating openings with varying widths at different heights. The upper portion has a larger width to facilitate filling, while the lower portion maintains appropriate dimensions for aspect ratio control. This dynamic dimensional variation allows both filling capability and aspect ratio control to be optimized simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the filling capability and reliability of semiconductor structures by ensuring better alignment and coverage of conductive layers, thereby improving the electrical performance and reducing defects in memory devices.
Implementation Method 1
A first implantation process is performed on the first conductive layer and the isolation structure, to form a doped portion in the first conductive layer and a doped portion in the isolation structure
Implementation Method 2
A first planarization process is performed, so that the top surfaces of the second conductive layer, the first conductive layer, and the isolation structure are aligned
Data Source
AI summary
A method of forming a semiconductor structure includes forming a mask layer on a substrate. The mask layer and the substrate include an opening. An isolation structure is formed in the opening. The mask layer is removed. A first conductive layer is formed on the isolation structure and the substrate. A first implantation process is performed on the first conductive layer and the isolation structure, to form a doped portion in the first conductive layer and a doped portion in the isolation structure. A second conductive layer is formed on the first conductive layer and the isolation structure. A first planarization process is performed, so that the top surfaces of the second conductive layer, the first conductive layer, and the isolation structure are aligned.