Semiconductor Fin Doping via Segmented Insulation Layers
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Solution Overview
Problem
Conventional semiconductor device manufacturing methods result in boron-containing ions diffusing into PMOS semiconductor fins during anti-punch-through ion implantation, affecting device performance by altering threshold voltage and saturation current.
Innovation Solution
A semiconductor device manufacturing method involving a first doping process in a NMOS semiconductor fin and a second doping process in a PMOS semiconductor fin, with specific ion implantation energies and doses, followed by removing a portion of the first insulation layer and forming a second insulation layer to reduce dopant diffusion into other fins, and applying an annealing treatment to activate the dopants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If anti-punch-through ion implantation is conducted deeper in NMOS fins to prevent punch-through, then punch-through prevention is improved, but dopant diffusion into STI and adjacent PMOS fins increases
Solution Approach 1:
The patent segments the ion implantation process into two separate steps: first implanting dopants into NMOS fins, then removing part of the insulation layer before implanting dopants into PMOS fins. This segmentation prevents dopants from diffusing into adjacent fins by isolating each implantation event spatially and temporally.
Solution Approach 2:
The patent extracts (removes) part of the first insulation layer between NMOS and PMOS fins after the first ion implantation. This extraction creates a physical barrier that prevents dopants from diffusing across the insulation layer into adjacent PMOS fins during subsequent processing.
2Ease of manufacture
If a single insulation layer is used to fill trenches, then manufacturing process is simplified, but dopant diffusion control between adjacent fins is insufficient
Solution Approach 1:
The patent divides the single insulation layer into two separate insulation layers: a first insulation layer filled before NMOS implantation, and a second insulation layer formed after removing part of the first layer and filling the remaining trench. This segmentation enables precise control of dopant diffusion while maintaining manufacturing feasibility.
Solution Approach 2:
The patent performs preliminary action by filling the first insulation layer and conducting NMOS ion implantation before removing part of the first insulation layer and forming the second insulation layer. This sequence of preliminary actions establishes the proper structural foundation for subsequent PMOS implantation with controlled dopant diffusion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces the diffusion of dopants into adjacent semiconductor fins, improving the performance of NMOS and PMOS devices by minimizing the mismatch in threshold voltage and saturation current.
Implementation Method 1
conducting a first doping process in the first semiconductor fin to form a first anti-punch-through region therein; conducting a second doping process in the second semiconductor fin to form a second anti-punch-through region therein
Implementation Method 2
applying an annealing treatment to activate the dopants
Data Source
AI summary
A semiconductor device manufacturing method is presented. The manufacturing method includes providing a semiconductor structure, comprising: a substrate, a plurality of semiconductor fins comprising a first semiconductor fin and a second semiconductor fin on the substrate, a plurality of trenches surrounding the semiconductor fins, and a first insulation layer filling the trenches; conducting a first doping process in the first semiconductor fin to form a first anti-punch-through region therein; removing at least a portion of the first insulation layer from the trenches; forming a second insulation layer filling a portion of the trenches not filled by the first insulation layer; and conducting a second doping process in the second semiconductor fin to form a second anti-punch-through region therein. This inventive concept reduces the chance of a dopant in the first doping process diffusing into the second semiconductor fin.