Semiconductor Device Fin-FET Gate-All-Around Hybrid Structure
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Solution Overview
Problem
As semiconductor devices increase in integration density, they face challenges such as leakage currents and short channel effects in field effect transistor devices due to decreasing size, which affect their reliability and performance.
Innovation Solution
A semiconductor device and method that simultaneously form a fin field effect transistor (FET) and a gate-all-around FET, with a fin-FET in a high-voltage region for body contact and a gate-all-around FET in a low-voltage region to suppress narrow channel effects, using a substrate with alternating layers of different semiconductor materials for the channel and source/drain regions, and forming gate electrodes that cover the channel regions from multiple sides.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If field effect transistor devices decrease in size to increase integration density, then integration density is improved, but leakage currents and short channel effects occur affecting reliability
Solution Approach 1:
The patent segments the semiconductor device into distinct high-voltage and low-voltage regions, each with appropriately sized transistors. The high-voltage region contains larger transistors that avoid short channel effects, while the low-voltage region contains smaller transistors optimized for density. This spatial segmentation allows high integration density overall while maintaining reliability in each region through appropriate device sizing.
Solution Approach 2:
The patent applies local quality by giving different regions different transistor characteristics. The high-voltage region uses larger transistors with dimensions that prevent short channel effects, while the low-voltage region uses smaller transistors for higher density. Each region's transistor size and structure are locally optimized for its specific voltage requirements, resolving the contradiction between overall density and local reliability.
2Reliability
If fin-FET structure is used in high-voltage region, then body contact is achieved for improved reliability, but device complexity increases
Solution Approach 1:
The patent segments the device structure into fin-FET regions for body contact and gate-all-around FET regions for simplified structure. The fin-FET structure with its vertical fins provides body contact and improved reliability in the high-voltage region, while the gate-all-around structure provides a simpler alternative in the low-voltage region. This segmentation achieves reliability where needed without unnecessarily complicating the entire device.
Solution Approach 2:
The patent applies local quality by using fin-FET structure specifically in the high-voltage region where body contact is critical for reliability, while using gate-all-around FET structure in the low-voltage region where such complexity is less critical. Each structure is locally applied based on the specific reliability requirements of that region, achieving body contact reliability where needed while avoiding unnecessary complexity elsewhere.
3Reliability
If gate-all-around FET structure is used in low-voltage region, then narrow channel effects are suppressed, but manufacturing complexity increases
Solution Approach 1:
The patent segments the device into regions using different gate structures. The gate-all-around FET structure is applied in the low-voltage region where narrow channel effects are problematic, providing superior suppression of these effects. This is combined with fin-FET structures in other regions, creating a segmented approach that achieves narrow channel effect suppression where needed without applying the complex structure universally, thereby managing manufacturing complexity.
Solution Approach 2:
The patent applies local quality by using gate-all-around FET structure specifically in the low-voltage region where narrow channel effects are the primary concern, while using simpler fin-FET structures in high-voltage regions where body contact is more critical. This localized application achieves narrow channel effect suppression in the appropriate region while avoiding unnecessary manufacturing complexity in regions where it is less critical.
4Manufacturing precision
If selective epitaxial growth or SOI wafers are used to form different transistor structures, then manufacturing precision is improved, but ease of manufacture decreases
Solution Approach 1:
The patent segments the fabrication process into standard CMOS steps that can form both fin-FET and gate-all-around FET structures using the same process flow. By segmenting the device into regions that can be formed simultaneously through standard processes rather than requiring specialized processes like selective epitaxial growth or SOI wafer processing, the patent achieves the necessary structural precision while maintaining ease of manufacture through conventional CMOS compatibility.
Solution Approach 2:
The patent applies universality by designing a fabrication process that uses standard CMOS steps to form both fin-FET and gate-all-around FET structures. The same deposition, etching, and patterning processes can create both transistor types, making the manufacturing process universal and compatible with conventional CMOS lines. This eliminates the need for specialized processes like selective epitaxial growth or SOI wafer processing, achieving structural precision through standard processes that are easier to manufacture.
Data Source
AI summary
A method of fabricating a semiconductor device includes preparing a substrate including a first region and a second region, sequentially forming a first semiconductor layer and a second semiconductor layer on the first and second regions, patterning the first and second semiconductor layers to form a lower semiconductor pattern and an upper semiconductor pattern on each of the first and second regions, selectively removing the lower semiconductor pattern on the second region to form a gap region, and forming gate electrodes at the first and second regions, respectively.