Semiconductor Fin Structure for Thick-Dielectric GAA I/O Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of input/output transistors into nanostructure transistor manufacturing processes is challenging due to the need for a gate dielectric layer with a great effective oxide thickness, particularly in gate-all-around (GAA) transistors, where scaling down complicates the formation of such transistors and maintains high on-current requirements.
Innovation Solution
The solution involves utilizing the lower fin element of a fin structure as a gate electrode layer and replacing the lowermost semiconductor layer with a gate dielectric layer of enhanced thickness, allowing for the integration of input/output transistors within the manufacturing process for nanostructure transistors, thereby meeting the requirements for effective oxide thickness and on-current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional GAA device fabrication processes are used, then nanowire channel structures can be formed, but integration of fabrication around the nanowire becomes challenging and gate dielectric layer thickness is insufficient
Solution Approach 1:
The fin structure is formed in advance before the nanowire channel structures are created. This preliminary fin structure serves as a pre-positioned gate dielectric layer formation template, allowing the gate dielectric layer to be deposited conformally on the fin structure surfaces. This preliminary action ensures that when the nanowire channels are subsequently formed around the fin structure, the gate dielectric layer is already in place with sufficient thickness, eliminating the need for complex post-formation gate dielectric integration.
Solution Approach 2:
The fin structure acts as an intermediary element between the substrate and the nanowire channel structures. This intermediary fin structure provides a stable platform for forming the gate dielectric layer with controlled thickness, and subsequently serves as a mold or template for creating the gate-all-around structures. The intermediary fin structure simplifies the overall fabrication process by decoupling the gate dielectric formation from the nanowire formation steps.
2Productivity
If device dimensions are scaled down to improve production efficiency and lower costs, then manufacturing efficiency improves, but process complexity increases
Solution Approach 1:
The fin structure serves multiple functions in the fabrication process: it acts as a support structure during nanowire formation, provides the template for gate dielectric layer deposition, serves as a mold for creating gate-all-around structures, and ultimately becomes part of the finished transistor structure. This multi-functionality reduces the number of separate fabrication steps needed, thereby simplifying the overall process despite device scaling.
Solution Approach 2:
The fabrication process employs a nested structure where the fin structure is formed first, then nanowire channels are formed around it, followed by gate dielectric and gate electrode layers that wrap around the nanowires. This nested approach allows each component to be formed in a logical sequence with previous structures serving as templates or molds for subsequent structures, reducing process complexity while enabling aggressive scaling.
Data Source
AI summary
A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes alternately stacking first sacrificial layers and first channel layers. The method also includes forming source/drain features on opposite sidewalls of the fin structure, etching the fin structure to form gate recesses in the fin structure, removing the first sacrificial layers of the fin structure from the gate recesses, thereby forming first gaps exposing the first channel layers, and forming a gate stack in the gate recesses and the first gaps.