Semiconductor Fin Gate Electrode Formation Process
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Solution Overview
Problem
The manufacturing of electronic devices with semiconductor fins and dual gate electrodes is challenging due to difficulties in achieving minimum spacing in lithography and the complexity of additional masking layers required for separation processes, which increases costs and integration issues.
Innovation Solution
A process involving the formation of a conductive member over the semiconductor fin, followed by reacting a portion to form independent gate electrodes, and modifying the masking layer to allow for the integration of single and dual-gated components without additional operations, enabling independent control of gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate first and second masking members are formed with a gap between them prior to etching gate electrode layer, then gate electrodes can be formed on semiconductor fin, but the width of the fin and distance between sides makes it difficult to achieve minimum spacing for lithography process
Solution Approach 1:
The single masking member is segmented into two separate masking members (first and second masking members) that are formed at different times. The first masking member forms the initial gate electrode, and the second masking member forms the additional gate electrode. This segmentation allows each masking member to be formed with adequate spacing requirements, avoiding the lithography resolution issues that would arise from attempting to form both gates simultaneously with minimum spacing.
Solution Approach 2:
The first gate electrode and its associated masking member are formed in advance before the second gate electrode and masking member are formed. This preliminary action allows the first gate structure to be established with proper dimensions and spacing, and then the second gate can be added subsequently without compromising the lithography resolution of either gate.
2Manufacturing precision
If a single conductive member is formed over the fin-type structure and then separated into two gate electrodes using additional masking layer and separation etch process, then dual gate electrodes can be formed, but overlay issues arise and additional masking layers add complexity and expense
Solution Approach 1:
Instead of forming one continuous conductive member and then separating it, the process segments the gate formation into two separate conductive member formation steps. Each step uses its own masking member, eliminating the need for a second masking layer to protect gate portions during separation. This segmentation removes the overlay issues and reduces the total number of masking layers required.
Solution Approach 2:
The first conductive member is formed in advance and established as a complete gate electrode before the second conductive member is formed. This preliminary formation eliminates the need for subsequent separation processes and additional masking layers that would be required if a single continuous conductive member were formed first and then divided.
3Ease of manufacture
If chemical mechanical planarization is used to separate conductive member, then additional masking operation is avoided, but all gate members at same elevation separate at substantially the same time and integration of chemical mechanical planarization is difficult and expensive
Solution Approach 1:
The gate formation process is segmented into separate steps for each gate electrode, with each gate formed by its own conductive member deposition and patterning sequence. This segmentation allows independent control of each gate's formation timing and geometry, eliminating the need for chemical mechanical planarization to separate simultaneously-formed gates. Each gate can be formed at different elevations and with different timing requirements.
Solution Approach 2:
The first gate electrode is formed in advance with its complete structure (conductive member and associated dielectric layers) before the second gate electrode is formed. This preliminary action allows the first gate to be established at its final elevation and configuration, and then the second gate can be added subsequently without requiring planarization to separate them.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces costs, and allows for easier integration of single-gated and dual-gated components on a single integrated circuit by eliminating the need for additional masking layers and overlay issues.
Implementation Method 1
reacting a portion to form independent gate electrodes
Data Source
AI summary
An electronic device can include a semiconductor fin with a first gate electrode adjacent to a first wall, and a second gate electrode adjacent to a second wall. In one embodiment, a conductive member can be formed overlying the semiconductor fin, and a portion of the conductive member can be reacted to form the first and second gate electrodes. In another embodiment, a patterned masking layer can be formed including a masking member over a gate electrode layer, and portion of the masking member overlying the semiconductor fin can be removed. In still another embodiment, a first fin-type transistor structure can include the semiconductor fin, the first and second gate electrodes, and a first insulating cap. The electronic device can also include a second fin-type transistor structure having a second insulating cap thicker than the first insulating cap.