Semiconductor Fin Structure With Co-Planar Sidewalls to Prevent Gate Shorts
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Solution Overview
Problem
The complexity of processing and manufacturing semiconductor integrated circuits (ICs) has increased due to scaling down processes, leading to issues such as gate electrode layer defects and electrical shorts between the gate electrode layer and the source/drain region.
Innovation Solution
A method is employed to form a semiconductor device structure by alternately stacking first and second semiconductor layers, removing edge portions of the second semiconductor layers to ensure co-planar side surfaces, and performing thermal processes to expand these layers laterally, thereby reducing defects and electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down process is used to increase functional density, then production efficiency is improved and costs are lowered, but processing complexity increases leading to gate electrode layer defects and electrical shorts
Solution Approach 1:
The patent applies preliminary action by performing a recessing process on the second semiconductor layer before forming the gate electrode layer. This advance preparation creates a stepped structure that prevents subsequent electrical shorts between the gate electrode and source/drain regions, thereby resolving the reliability issue that arises from scaling down processes
Solution Approach 2:
The patent segments the semiconductor layer structure by creating a stepped configuration where the second semiconductor layer is recessed relative to the first semiconductor layer. This segmentation separates the gate electrode formation area from the source/drain region, preventing electrical shorts while maintaining the high functional density achieved through scaling down
2Productivity
If scaling down process is used to increase functional density, then production efficiency is improved and costs are lowered, but processing complexity increases leading to manufacturing difficulties
Solution Approach 1:
The recessing process is performed as a preliminary step before gate electrode formation, simplifying the overall manufacturing process by pre-establishing the stepped structure. This eliminates the need for complex alignment and positioning operations during subsequent processing steps
Solution Approach 2:
The patent applies local quality by creating a stepped structure only in specific regions where the second semiconductor layer is recessed. This localized structural modification simplifies processing in critical areas while maintaining the overall device architecture required for high functional density
3Reliability
If conventional fin structure is used with alternating semiconductor layers, then device functionality is achieved, but lateral expansion during isolation region formation causes non-co-planar side surfaces resulting in gate electrode layer defects
Solution Approach 1:
The second semiconductor layer is recessed in advance before the isolation region formation process. This preliminary action anticipates and prevents the lateral expansion issue, ensuring that when the isolation regions are formed and thermal processes cause lateral expansion, the side surfaces remain co-planar
Solution Approach 2:
The recessing process applies preliminary anti-action by removing material from the second semiconductor layer before lateral expansion occurs. This creates a compensatory depression that counteracts the subsequent lateral expansion, maintaining co-planar side surfaces and preventing gate electrode layer defects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes gate electrode layer defects and electrical shorts, enhancing the manufacturing process by providing a larger process window for removing sacrificial gate structures and reducing the risk of electrical shorts between the gate electrode and source/drain regions.
Implementation Method 1
During the subsequent process to form isolation regions, the second semiconductor layers expend laterally, so side surfaces of the second semiconductor layers and side surfaces of the first semiconductor layers are substantially co-planar
Data Source
AI summary
Embodiments of the present disclosure provide methods for forming semiconductor device structures. The method includes forming a fin structure from a substrate, and the fin structure includes alternating first and second semiconductor layers. The method further includes removing edge portions of each of the second semiconductor layers, depositing an insulating material around the fin structure, performing a thermal process to expand the second semiconductor layers laterally, forming a sacrificial gate structure over a portion of the fin structure, recessing an exposed portion of the fin structure, and forming a source/drain region over the recessed portion of the fin structure.