Semiconductor Device Fin Height Segmentation for Speed Power Trade-off
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Solution Overview
Problem
Conventional semiconductor devices, including fin field effect transistors, face challenges in optimizing both high-frequency and low-power performance simultaneously due to the interdependence of fin heights and operating frequencies, where increasing fin height to enhance frequency leads to increased power consumption, negatively impacting low-power device performance.
Innovation Solution
A semiconductor device and fabrication method that differentiate between high-frequency and low-power logic standard cells by varying fin heights and operating frequencies, with high-frequency cells having taller, denser fins and low-power cells having shorter, less dense fins, allowing for independent optimization of performance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If fin height is increased to enhance operating frequency, then high-frequency performance is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by differentiating fin heights across different functional blocks within the same semiconductor device. High-frequency blocks utilize taller fins to achieve higher operating frequencies, while low-power blocks employ shorter fins to minimize power consumption. This localized differentiation allows each block to be optimized for its specific functional requirements without compromising the other, effectively resolving the contradiction between speed and energy usage.
2Adaptability or versatility
If conventional fin field effect transistor structure is used, then device complexity is reduced, but performance optimization for both high-frequency and low-power modes is limited
Solution Approach 1:
The patent segments the semiconductor device into distinct functional blocks, each with tailored fin configurations. By dividing the device into high-frequency blocks and low-power blocks with different fin heights, the structure enables independent optimization of performance characteristics for each segment. This segmentation approach increases adaptability and versatility without introducing excessive complexity, as each block can be designed and optimized separately according to its specific performance requirements.
Data Source
AI summary
The present disclosure provides a semiconductor device manufacturing method. The method includes: providing a semiconductor substrate, including a high-frequency-block group and a low-power-block group; forming high-frequency-type logic standard cells on the high-frequency-block group of the semiconductor substrate. The high-frequency-type logic standard cells have a high-frequency-type cell height, a high-frequency-type operating frequency, and a high-frequency-type power. The method further includes forming low-power-type logic standard cells on the low-power-block group of the semiconductor substrate. The low-power-type logic standard cells have a low-power-type cell height, a low-power-type operating frequency, and a low-power-type power.