Semiconductor Active Pattern Fin Height Variation for Channel Strain
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Solution Overview
Problem
As semiconductor devices are scaled down, their operational properties deteriorate due to increased size reduction, leading to challenges in maintaining high performance.
Innovation Solution
A semiconductor device design featuring a substrate with an active pattern, gate structure, and source/drain regions, where the active pattern has specific surface shapes and orientations, and device isolation patterns, along with epitaxial source/drain regions and buffer patterns formed from germanium-containing materials, to enhance channel and resistance properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the size of MOS-FET is reduced to accelerate design rule reduction, then the scale-down of semiconductor device is achieved, but the operational properties of semiconductor device deteriorate
Solution Approach 1:
The active pattern is divided into multiple fin structures (first fin structure, second fin structure, third fin structure) with different heights and configurations. This segmentation allows each fin to contribute differently to device performance, enabling continued scaling while maintaining operational properties through the combined effect of multiple structures rather than relying on a single scaled-down transistor.
Solution Approach 2:
The patent introduces vertical dimension variation by creating fins of different heights (first fin structure with first height, second fin structure with second height greater than first height, third fin structure with third height). This multi-level vertical structure adds a new dimension to the traditionally planar or single-height fin design, allowing improved channel control and performance without simply reducing horizontal dimensions.
2Reliability
If the height of source/drain regions is reduced to minimize strain on channel, then channel property is improved, but contact resistance increases
Solution Approach 1:
Different source/drain regions are assigned different heights locally - the first source/drain region has first height, the second source/drain region has second height greater than first height. This local differentiation allows the taller second source/drain region to provide lower contact resistance while the overall structure maintains controlled strain on the channel through the multi-fin configuration.
Solution Approach 2:
The patent resolves the height contradiction by introducing multiple vertical levels through different fin structures. The multi-height configuration allows source/drain regions to access different vertical positions, enabling optimization of both contact resistance (through taller regions providing better contact) and channel strain (through distributed geometry across multiple fins and heights).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves channel properties and resistance by reducing height variations in the source/drain regions, thereby minimizing strain on the channel and reducing contact resistance, leading to enhanced performance and stability of the semiconductor device.
Implementation Method 1
minimizing strain on the channel
Implementation Method 2
epitaxial source/drain regions and buffer patterns formed from germanium-containing materials
Data Source
AI summary
A semiconductor device includes a substrate provided with an active pattern; a gate structure provided on the active pattern to cross the active pattern; and source/drain regions provided at both sides of the gate structure. The active pattern includes a first region below the gate structure and second regions at both sides of the gate structure. A top surface of each of the second regions is lower than that of the first region. The source/drain regions are provided on the second regions, respectively, and each of the source/drain regions covers partially both sidewalls of each of the second regions.