Semiconductor Fin Formation via Layer Segmentation and Insulation
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Solution Overview
Problem
The formation of semiconductor fins with varying material characteristics for transistors is complex and costly, and existing double semiconductor-on-insulator substrates face integration issues with lithography and planarization due to differences in elevation between channel regions.
Innovation Solution
A process involving a base layer, multiple semiconductor layers, and insulating layers is used to form semiconductor fins, where the layers are spaced apart and selectively removed to create fins with different heights and materials, allowing for the formation of semiconductor fins with varying dopant types and crystal orientations, and the use of buried insulating layers to facilitate planarization and lithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If additional processing is used to selectively thin semiconductor regions to form fins of different heights, then fins with varying heights can be formed, but manufacturing complexity increases considerably
Solution Approach 1:
The patent divides the semiconductor structure into multiple discrete layers (first semiconductor layer, second semiconductor layer, insulating layers) that can be independently formed and processed. This segmentation allows each layer to be optimized separately and simplifies the overall manufacturing process by enabling standard fabrication techniques to be applied to each layer independently rather than requiring complex selective thinning processes.
Solution Approach 2:
The patent transitions from a two-dimensional planar structure to a three-dimensional stacked structure by adding vertical layering. Multiple semiconductor layers are stacked above each other with insulating layers in between, creating fins of different heights through the vertical dimension rather than through complex lateral processing. This dimensional approach simplifies manufacturing by using standard deposition and etching processes.
2Reliability
If a double semiconductor-on-insulator substrate is used to address carrier mobility issues, then carrier mobility in channel regions is improved, but integration with lithography and planarization processes becomes problematic due to elevation differences
Solution Approach 1:
The patent applies different material properties and layer configurations to different regions of the device. Specifically, different semiconductor layers can have different crystal orientations, dopant types, or materials tailored to specific transistor locations. This local customization allows optimization of carrier mobility in channel regions while maintaining compatibility with standard manufacturing processes through selective formation of layers only where needed.
Solution Approach 2:
The patent performs preliminary formation of multiple semiconductor layers and insulating layers before final fin formation and device completion. By pre-establishing the layered structure with appropriate thicknesses and material properties, the patent enables subsequent lithography and planarization processes to proceed without elevation-related issues, as the preliminary layers are designed to work within the constraints of standard process equipment.
Data Source
AI summary
An electronic device can include a base layer, a semiconductor layer, and a first semiconductor fin spaced apart from and overlying a semiconductor layer. In a particular embodiment, a second semiconductor fin can include a portion of the semiconductor layer. In another aspect, a process of forming an electronic device can include providing a workpiece that includes a base layer, a first semiconductor layer that overlies and is spaced apart from a base layer, a second semiconductor layer that overlies, and an insulating layer lying between the first semiconductor layer and the second semiconductor layer. The process can also include removing a portion of the second semiconductor layer to form a first semiconductor fin, and forming a conductive member overlying the first semiconductor fin.