Semiconductor Fin Structures for Logic and Peripheral Regions
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Solution Overview
Problem
The existing gate-all-around structures in semiconductor devices face challenges in achieving optimal performance due to high voltage requirements in peripheral devices, where the thin gate dielectric layer is prone to breakdown, and forming a work function layer in tight spaces between fin layers is difficult, affecting the overall device performance.
Innovation Solution
A method is developed to form a semiconductor device with a gate-all-around structure in the logic region and a multi-gate device of a single material in the peripheral region, involving the formation of initial and modified fins, isolation structures, and gate dielectric layers of varying thicknesses to enhance control and performance, including the use of epitaxial growth for modified fins and specific etching processes to create trenches for improved fin structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a thin gate dielectric layer is used in gate-all-around structures to reduce device size, then device integration density is improved, but the gate dielectric layer becomes prone to breakdown under high voltage in peripheral devices
Solution Approach 1:
The patent applies different gate dielectric layer thicknesses to different regions of the semiconductor device. Specifically, the first gate dielectric layer in the logic region has a first thickness, while the second gate dielectric layer in the peripheral region has a second thickness that is greater than the first thickness. This local differentiation allows thin gate dielectric layers in logic regions for high density while using thicker gate dielectric layers in peripheral regions for high voltage tolerance, resolving the contradiction between integration density and breakdown resistance.
2Reliability
If gate-all-around structures are used to control short channel effect, then device performance is improved, but forming work function layer in tight spaces between fin layers becomes difficult
Solution Approach 1:
The patent segments the semiconductor device into distinct logic regions and peripheral regions with different fin structures. The logic region contains fins with alternating first and second materials that form gate-all-around structures for excellent short channel control. The peripheral region contains modified fins made of single material that are easier to manufacture. This spatial segmentation allows each region to be optimized independently, resolving the contradiction between short channel control performance and manufacturing ease.
Solution Approach 2:
The patent implements different fin structures in different regions: the logic region has alternating first fin layers and second fin layers for gate-all-around control, while the peripheral region has modified fins of single material for easier work function layer formation. This local quality differentiation allows the work function layer to be easily formed in peripheral regions while maintaining excellent short channel control in logic regions.
3Adaptability or versatility
If multiple devices with multiple functions are integrated on a single chip, then device functionality is improved, but the performance of individual devices may be compromised
Solution Approach 1:
The patent applies different structural configurations to different functional regions on the same chip. The logic region uses gate-all-around structures with alternating fin layers for high-performance logic operations, while the peripheral region uses modified single-material fins for input/output devices. This allows each device type to be optimized for its specific function while being integrated on a single chip, resolving the contradiction between versatility and individual device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of semiconductor devices by allowing for thicker gate dielectric layers in peripheral regions without compromising the quality of the work function layer, enhancing control over the channel region and integrating multiple functions on a single chip effectively.
Implementation Method 1
The method may also include forming a modified fin made of a single material in the trench
Data Source
AI summary
Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having a logic region and a peripheral region; forming initial fins on the semiconductor substrate; forming a protective layer on the sidewall surfaces of the initial fin in the peripheral region; removing the initial fin in the peripheral region to form a trench with a bottom surface lower than a top surface of the isolation structure; forming a modified fin made of a single material in the trench; removing the protective layer; forming a first gate structure having a first gate dielectric layer and surrounding the first fin layers in the logic region across the initial fin in the logic region; and forming a second gate structure having a second gate dielectric layer with a thickness greater than a thickness of the first gate dielectric layer across the modified fins.