Semiconductor Fin and Pillar Structure Parasitic Capacitance Reduction
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Solution Overview
Problem
The increasing integration of semiconductor integrated circuits, particularly those using MOS transistors, faces challenges in suppressing leak currents and reducing parasitic capacitance due to nano-scale transistor sizes, which complicates the production process and requires innovative methods for forming SGTs with metal gates and insulating films.
Innovation Solution
A method for producing semiconductor devices involves forming fin-shaped and pillar-shaped semiconductor layers on a substrate, using a gate last process, and employing a metal gate last process to decrease parasitic capacitance between the gate line and substrate, while enabling the production of two transistors from a single dummy pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal gate is used instead of polysilicon, then the resistance of the gate electrode is decreased and depletion is suppressed, but the production process becomes more complex due to metal contamination concerns
Solution Approach 1:
A metal gate protective film is formed over the metal gate electrode before subsequent processing steps. This protective film prevents metal contamination of underlying layers during etching and other high-temperature processes, allowing the metal gate to be formed early in the process rather than last, thus simplifying the overall production process while maintaining metal gate performance benefits
2Reliability
If a first insulating film is formed around the fin-shaped semiconductor layer, then the parasitic capacitance between gate line and substrate is decreased, but the manufacturing process becomes more complex
Solution Approach 1:
The first insulating film formation process is merged with the spacer formation process. The same spacer material and deposition/etching steps that create the sidewall spacers also form the first insulating film around the fin-shaped semiconductor layer, reducing parasitic capacitance without adding separate manufacturing steps
Solution Approach 2:
The spacer structure serves multiple functions: it acts as a mask for etching the fin-shaped semiconductor layer, provides sidewall protection, and simultaneously forms the first insulating film that reduces parasitic capacitance between the gate line and substrate
3Productivity
If two transistors are formed from a single dummy pattern using sidewalls, then the productivity is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The etching process is made selective to different regions: the fin-shaped semiconductor layer is etched with specific dimensions controlled by the spacer width, while the pillar-shaped semiconductor layer is formed with different dimensions through separate etching steps. This local quality control allows high productivity from single dummy patterns while maintaining precise dimensional control for each transistor type
Data Source
AI summary
A method for producing a semiconductor device includes forming a first fin-shaped semiconductor layer and a second fin-shaped semiconductor layer on a substrate using a sidewall formed around a dummy pattern on the substrate. A first insulating film is formed around the first fin-shaped semiconductor layer and the second fin-shaped semiconductor layer. A first pillar-shaped semiconductor layer is formed in an upper portion of the first fin-shaped semiconductor layer, and a second pillar-shaped semiconductor layer is formed in an upper portion of the second fin-shaped semiconductor layer.