Semiconductor Device Manufacturing Method for Fin and Planar Transistors
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Solution Overview
Problem
Conventional techniques face difficulties in simultaneously forming fin type and planar MOSFETs on the same semiconductor substrate using a common process, as they require different etching rates and mask materials, making it challenging to achieve high integration and precise pattern formation.
Innovation Solution
A manufacturing method involving the sequential formation of mask films and etching processes, where different etching rates and materials are used to selectively remove layers, allowing for the formation of fin type and planar transistors by protecting specific areas and using barrier films to maintain precision, enabling the creation of both types of transistors on the same substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional techniques are used to form fin type and planar transistors, then different etching rates and mask materials are required, but it becomes difficult to separately form both transistor types by a common process
Solution Approach 1:
The substrate is divided into a first area for fin type transistors and a second area for planar transistors. Different mask film structures are formed in each area: a multi-layer mask structure (first mask film, second mask film, third mask film) in the first area and a simpler mask structure in the second area, allowing each region to be optimized for its specific transistor type while using a common overall process
Solution Approach 2:
Different mask film configurations are applied to different areas of the substrate according to the specific requirements of each transistor type. The first area receives a complex multi-layer mask structure with specific etching rates and material properties, while the second area receives a different mask structure, enabling localized optimization without requiring completely separate processing lines
2Manufacturing precision
If different etching rates are used for fin type and planar transistors, then precise pattern formation is achieved, but it becomes challenging to use a common process for both transistor types
Solution Approach 1:
A second mask film is introduced as an intermediary layer between the first mask film and the third mask film in the first area. This intermediate layer has different etching rate characteristics that enable precise pattern formation for fin type transistors, while the overall multi-layer mask structure can still be processed using common etching equipment and processes applicable to both transistor types
3Manufacturing precision
If fin structures are formed on semiconductor substrate, then channel width is increased without increasing element area, but the fin structures become vulnerable to damage during subsequent etching processes
Solution Approach 1:
The first mask film and second mask film are formed on the fin structures before the etching process that forms the gate electrode. These mask films serve as protective layers that prevent damage to the fin structures during subsequent etching steps, while still allowing precise pattern formation for the channel region
Solution Approach 2:
The second mask film acts as a protective intermediary layer between the fin structures and the etching process. This intermediate mask layer has controlled etching rate characteristics that protect the fin structures from damage while enabling precise definition of the channel width, and is removed after serving its protective function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the precise formation of both fin type and planar transistors on the same substrate, achieving high integration and preventing damage to the fin structures during etching, thus enabling the production of advanced semiconductor devices with improved integration and performance.
Implementation Method 1
The removing is performed by etching in a condition in which an etching rate of the upper mask member and an etching rate of the lower mask member are higher than an etching rate of the barrier member while protecting a side surface of the lower mask member
Implementation Method 2
selectively removing the conductive film by performing etching in a condition in which an etching rate of the conductive film is higher than the etching rate of the lower mask member
Data Source
AI summary
According to one embodiment, a manufacturing method of a semiconductor device includes forming a lower mask film on a semiconductor substrate. The method includes forming a barrier film in a first area. The method includes forming an upper mask film. The method includes removing an upper mask member and leaving a lower mask member in the first area and removing the upper mask member and the lower mask member in the second area. The removing is performed by etching in a condition in which an etching rate of the upper mask member and an etching rate of the lower mask member are higher than that of the barrier member. The method includes forming a conductive film. The method includes selectively removing the conductive film by performing etching in a condition in which an etching rate of the conductive film is higher than that of the lower mask member.