Semiconductor Fin Structure Reducing Plug Gate Capacitance
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Solution Overview
Problem
Current semiconductor structures face challenges in reducing parasitic capacitance between conductive plugs and gate structures, which affects alternating current performance due to the large effective area between them.
Innovation Solution
A method is introduced that involves forming a first dielectric layer exposing the fin, followed by an etch stop layer covering the fin and source/drain doping region, and a second dielectric layer on top, allowing a conductive plug to penetrate through, thereby reducing the height of the conductive plug and minimizing the effective area between the plug and the gate structure, thus reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional conductive plug structure is used, then the connection between metal layers is achieved, but the parasitic capacitance between the conductive plug and gate structure is large due to the large effective area
Solution Approach 1:
The patent introduces a first dielectric layer that exposes the top of the fin, creating a new spatial dimension for the conductive plug formation. This allows the conductive plug to penetrate through the second dielectric layer and etch stop layer while being positioned to span the fin, thereby reducing the effective area between the conductive plug and gate structure in the vertical dimension, which reduces parasitic capacitance while maintaining electrical connection functionality
2Object-generated harmful factors
If the conductive plug height is reduced, then the parasitic capacitance is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary actions by forming the first dielectric layer to expose the fin top, then forming the etch stop layer conformally covering the fin and source/drain doping region. This preliminary structuring establishes precise reference planes before conductive plug formation, enabling accurate positioning and depth control of the conductive plug, thereby reducing parasitic capacitance while maintaining manufacturing precision through pre-established geometric constraints
3Manufacturing precision
If a trench conductive plug structure is introduced, then the critical dimension and overlay precision requirements are reduced, but the parasitic capacitance between conductive plug and gate structure increases
Solution Approach 1:
The patent applies local quality by creating a specific structural configuration where the conductive plug spans the fin and connects to source/drain doping regions while the first dielectric layer exposes the fin top. This localized structural arrangement reduces the effective area between the conductive plug and gate structure in critical regions, thereby reducing parasitic capacitance while maintaining the trench conductive plug's advantage of reduced overlay precision requirements
Data Source
AI summary
A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a substrate and a fin, a gate structure being formed on the substrate, the gate structure spanning the fin and covering a partial sidewall and a partial top of the fin, and a source/drain doping region being formed in the fin on both sides of the gate structure; forming a first dielectric layer on the substrate, the first dielectric layer exposing the top of the fin; forming an etch stop layer to conformally cover the first dielectric layer and the fin and the source/drain doping region exposed by the first dielectric layer; forming a second dielectric layer on the etch stop layer; and forming a conductive plug penetrating through the second dielectric layer and the etch stop layer, the conductive plug spanning the fin, and the conductive plug being connected to the source/drain doping region. Under the action of a first dielectric layer, the effective area between a conductive plug and a gate structure is reduced, and the parasitic capacitance between a conductive plug and a device gate structure is reduced accordingly.