Semiconductor Fin Structure with Expanded PN Junction Interface
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Solution Overview
Problem
As semiconductor devices shrink, the reduced critical dimension of PN junctions in diodes leads to a decrease in interface area, resulting in reduced performance due to smaller contact resistance and on-current.
Innovation Solution
A semiconductor structure and fabrication method involving the formation of fins on a substrate with doped layers of opposite conductivity types, where the interface size between these layers is greater than the fin width, enhancing the contact area and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the critical dimension of semiconductor devices is reduced to increase integration level, then more devices can be formed on a single chip, but the interface area of the PN junction is reduced leading to decreased device performance
Solution Approach 1:
The patent transitions from a planar PN junction to a three-dimensional structure by forming fins on the semiconductor substrate. The doped layers are formed on these fins, creating a vertical interface structure. This dimensional change allows the interface area to be increased along the vertical dimension while maintaining a small critical dimension in the horizontal plane, thus resolving the contradiction between high integration and sufficient interface area.
Solution Approach 2:
The patent forms a first doped layer containing a first type of doping ions within the fin structure, and then forms a second doped layer containing a second type of doping ions on the first doped layer. This nested arrangement of oppositely doped layers creates an extended interface area within the confined fin structure, effectively increasing the PN junction interface area without increasing the critical dimension.
2Productivity
If the critical dimension is reduced to allow more devices per chip, then manufacturing capacity increases, but contact resistance increases and on-current decreases due to smaller interface area
Solution Approach 1:
By forming vertical fins and stacking doped layers on these fins, the patent creates a three-dimensional interface structure. This vertical stacking approach increases the effective interface area for carrier transport without increasing the horizontal critical dimension, thereby maintaining low contact resistance and high on-current while enabling higher device density.
Solution Approach 2:
The patent uses composite doping structures with alternating layers of n-type and p-type doped regions. This composite structure creates multiple interfaces within the fin, increasing the total interface area available for carrier transport and improving electrical performance despite the reduced critical dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the area of the PN junction interface, thereby improving the performance of semiconductor diodes by enhancing on-current and overall device performance.
Implementation Method 1
A PN junction is often formed in the diode. Such a device allows a current to flow only along one direction; and blocks the flow of the current along another direction according to the direction of the external electric field.
Implementation Method 2
When the external electrical field is zero, the diffusion current induced by the carrier concentration difference at two sides of the PN junction and the drift current induced by the build-in field are equal
Implementation Method 3
When the external electrical field is zero, the diffusion current induced by the carrier concentration difference at two sides of the PN junction and the drift current induced by the build-in field are equal; and the PN junction is at an equilibrium state.
Data Source
AI summary
Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate having at least one diode region; forming at least one first fin on the semiconductor substrate in the diode region; forming a first doped layer containing a first type of doping ions having a first conductivity in the first fin; and forming a second doped layer doped containing a second type of doping ions having a second conductivity opposite to the first conductivity on the first doped layer. A size of an interface between the first doped layer and the second doped layer along a width direction of the first fin is greater than a width of the first fin.