Semiconductor FinFET Self-Aligned Punch-Through Stopper Leakage
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Solution Overview
Problem
Short channel effects in planar semiconductor devices lead to increased leakage current, which is difficult to control due to the fin's bottom being surrounded by the isolation layer, and introducing a Punch-Through Stopper (PTS) increases band-to-band leakage and junction capacitance.
Innovation Solution
A semiconductor device and manufacturing method involving a substrate with a well having different doping concentrations, a fin structure, an isolation layer exposing the fin, a sacrificial gate conductor layer, and a self-aligned PTS formed under the fin through a gate trench to reduce leakage current and capacitance, with the PTS being directly under the channel region and not under the source and drain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Punch-Through Stopper (PTS) is introduced to suppress leakage current, then leakage current between source and drain is reduced, but band-to-band leakage and junction capacitance increase
Solution Approach 1:
The patent applies local quality by creating a doping concentration gradient in the well structure, with higher doping concentration near the fin bottom and lower doping concentration toward the source/drain regions. This spatial variation in doping concentration allows the PTS function to be localized exactly where needed (under the fin) while avoiding the harmful effects in other regions (under source/drain), thus resolving the contradiction between leakage suppression and capacitance reduction.
2Stability of the object's composition
If the fin bottom is surrounded by isolation layer, then the fin structure is isolated, but gate control over the fin bottom is lost and leakage current increases
Solution Approach 1:
The patent changes the doping concentration parameter in the well region to create a gradient profile. By increasing the doping concentration near the fin bottom, the electrical properties of the well are modified to provide both isolation stability and improved gate control, allowing the gate to effectively control the fin bottom potential and suppress leakage current without compromising the isolation layer's stabilizing function.
Data Source
AI summary
Provided are a semiconductor device and a method of manufacturing the same. An example device may include: a substrate having a well formed therein, the well including a first section and a second section, wherein the first section has a lower doping concentration and is closer to a surface of the substrate than the second section; a fin structure formed on the surface of the substrate; an isolation layer formed on the surface of the substrate, wherein the isolation layer exposes a portion of the fin structure, which serves as a fin for the semiconductor device; a gate stack formed on the isolation layer and intersecting the fin, wherein a Punch-Through Stopper (PTS) is formed in only a region directly under a portion of the fin where the fin intersects the gate stack.