Semiconductor Fin Removal During Fabrication for Uniform Fin Geometry
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Solution Overview
Problem
Existing methods for forming integrated circuit structures with semiconductor fins face challenges in achieving uniform fin dimensions and preventing fin stubs, particularly as fin spacing and aspect ratios increase, leading to issues such as inconsistent widths and depths, and the formation of fin stubs.
Innovation Solution
A mid-process fin trim technique is employed, involving a selective etch stop layer and sacrificial fin cut mask layers to remove partially-formed fins, followed by a deep trench etch, ensuring uniform geometric dimensions and eliminating fin stubs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fin formation methods are used, then fins can be formed in the substrate, but uniform fin dimensions and consistent widths cannot be achieved, leading to width mismatches and fin stubs
Solution Approach 1:
The fin formation process is divided into multiple etching stages: a first anisotropic etch to create initial fin structures, followed by a second etch to remove fins in wide trenches. This segmentation allows precise control over fin dimensions and selective removal of fins where needed, achieving uniform fin geometry without requiring complex mask patterns
Solution Approach 2:
The method performs preliminary fin formation across the entire substrate before selectively removing fins in specific regions. By first creating all fins uniformly and then removing those in wide trenches through a second etch process, the method ensures that remaining fins have consistent dimensions and eliminates the need for complex preliminary masking to prevent fin formation in certain areas
2Productivity
If fin spacing and aspect ratios are increased, then more fins can be accommodated, but inconsistent widths and depths occur
Solution Approach 1:
The etching process is made dynamic by adjusting etch parameters between stages. The first anisotropic etch uses specific conditions to create fins of controlled height and width, while the second etch uses different parameters to selectively remove fins in wide trenches. This dynamic adjustment of etch conditions allows consistent fin dimensions even when spacing and aspect ratios vary across the substrate
Solution Approach 2:
The method changes physical and chemical parameters of the etching process between stages. By modifying etch selectivity, depth, and anisotropy ratios between the first and second etching steps, the process achieves uniform fin dimensions across varying spacings and aspect ratios, preventing width mismatches while maintaining high fin density
3Measurement precision
If hard mask layers are made narrower to improve patterning margins, then patterning precision improves, but fin formation control becomes more difficult
Solution Approach 1:
Instead of using narrow hard masks to define fin locations directly, the method inverts the approach by first forming fins across the entire substrate and then selectively removing them. This inversion allows use of broader, easier-to-form initial masks while achieving precise fin placement through the selective second etch process, maintaining patterning precision without sacrificing manufacturability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in integrated circuit structures with uniformly spaced and dimensioned semiconductor fins, reducing leakage and performance issues associated with fin stubs and width mismatches, while allowing for narrower hard mask usage and improved patterning process margins.
Implementation Method 1
a selective etch stop layer and sacrificial fin cut mask layers to remove partially-formed fins
Implementation Method 2
followed by a deep trench etch, ensuring uniform geometric dimensions and eliminating fin stubs
Data Source
AI summary
Techniques are disclosed for forming integrated circuit structures having a plurality of semiconductor fins, which in turn can be used to form non-planar transistor structures. The techniques include a mid-process removal of one or more partially-formed fins. The resulting integrated circuit structure includes a plurality of semiconductor fins having relatively uniform dimensions (e.g., fin width and trough depth). In an embodiment, the fin forming procedure includes partially forming a plurality of fins, using a selective etch stop built into the semiconductor structure in which the fins are being formed. One or more of the partially-formed fins are removed via sacrificial fin cut mask layer(s). After fin removal, the process continues by further etching trenches between the partially-formed fins (deep etch) to form portion of fins that will ultimately include transistor channel portion. A liner material may be deposited to protect the partially-formed fins during this subsequent deep trench etch.