Semiconductor Fin RRAM Integration via Dummy Gate Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing of RRAM devices adjacent to FinFETs requires precise alignment and processing control, which is challenging due to the small feature size and difficulty in implementing self-aligning contact processes, leading to increased complexity and manufacturing difficulties.
Innovation Solution
A method for manufacturing a semiconductor device involving the formation of a data storage layer and conductive material layer in an opening of an interlayer dielectric layer covering a semiconductor fin, with the use of dummy gates and etching processes to create a larger process window and avoid the need for self-aligning contact processes, facilitating easier implementation and compatibility with CMOS processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a small feature size is used for the data storage layer formation, then the integration density is improved, but the manufacturing precision requirement increases and processing control becomes more difficult
Solution Approach 1:
The patent introduces a dummy gate structure as an intermediary element to establish a reference alignment feature. The dummy gate serves as a mediator between the FinFET structure and the RRAM data storage layer, enabling precise alignment without requiring direct alignment between the small feature components. This intermediary reference structure allows the small feature size to be maintained while reducing the manufacturing precision burden.
Solution Approach 2:
The dummy gate is formed in advance before the data storage layer deposition. This preliminary action creates a pre-established alignment reference that guides subsequent processing steps. By performing the alignment reference creation beforehand, the patent enables better control over the final small feature dimensions and reduces the precision requirements during the actual data storage layer formation.
2Manufacturing precision
If self-aligning contact process is implemented, then the alignment precision is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent extracts the alignment function from the contact process itself and relocates it to the dummy gate structure. Instead of relying on complex self-aligning contact mechanisms, the alignment functionality is separated out and embodied in the simpler dummy gate reference structure. This extraction simplifies the contact formation process while maintaining high alignment precision.
Solution Approach 2:
The dummy gate creates a copied or replicated reference pattern that can be used to align subsequent layers. Rather than implementing complex self-aligning mechanisms, the patent uses a simplified copied reference structure from the dummy gate to guide the data storage layer and contact formation, reducing process complexity while achieving the desired alignment precision.
3Reliability
If a long vertical portion of slot contact is formed, then the electrical connection is improved, but the manufacturing difficulty increases
Solution Approach 1:
The dummy gate structure is formed in advance to establish the alignment reference before contact formation. This preliminary structure enables better control over the slot contact geometry, including the vertical portion dimensions, making the manufacturing of long vertical contacts more feasible by providing a pre-established alignment framework.
Solution Approach 2:
The dummy gate acts as an intermediary reference that facilitates the formation of the slot contact with the required long vertical portion. By providing a stable alignment reference, the dummy gate enables the precise formation of complex contact geometries that would otherwise be difficult to manufacture, thus improving electrical connection while managing manufacturing difficulty.
Data Source
AI summary
The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method may include: providing a semiconductor structure, where the semiconductor structure includes a semiconductor fin and an interlayer dielectric layer covering the semiconductor fin, the interlayer dielectric layer having an opening exposing a part of the semiconductor fin; forming a data storage layer at a bottom portion and a side surface of the opening; and filling a conductive material layer in the opening on the data storage layer. The present disclosure facilitate the manufacturing process of the semiconductor device and improves processing compatibility with the CMOS technology.