Semiconductor Fin Structures via Selective Etching
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in effectively forming fin-type structures with different materials for N-type and P-type field effect transistors, which requires precise control of etching processes to achieve stress-induced mobility enhancements while maintaining the complexity of multi-step fabrication processes.
Innovation Solution
A method involving the formation of a heterogeneous channel layer with silicon and silicon germanium alloy layers on a strain relaxed buffer layer, followed by sequential etching processes to create fin-type structures with specific depths and liner formations, allowing for simultaneous patterning of NFET and PFET structures with different materials, thereby enhancing carrier mobility without increasing transistor size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate etching processes are used for NFET and PFET fin structures, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the channel layer into heterogeneous segments (silicon layer for NFETs and SiGe alloy layer for PFETs) that can be selectively etched. This segmentation allows different materials to be processed differently while maintaining overall process integration, resolving the contradiction by enabling precise control of each transistor type through material differentiation rather than separate process flows.
Solution Approach 2:
The patent applies local quality by creating regions with different material compositions (silicon vs. SiGe alloy) in specific locations corresponding to NFET and PFET regions. This local material differentiation enables selective etching behavior in different areas of the same wafer, achieving manufacturing precision for both transistor types within a unified fabrication process.
2Reliability
If transistor size is increased to improve carrier mobility, then carrier mobility is improved, but productivity decreases
Solution Approach 1:
The patent changes the material composition parameter by introducing SiGe alloy layers with different germanium concentrations in different regions. This parameter change (material composition rather than geometric size) achieves carrier mobility enhancement without increasing transistor physical dimensions, thereby maintaining high transistor density and productivity.
Solution Approach 2:
The patent uses composite materials (silicon and SiGe alloy layers) with different properties to achieve carrier mobility enhancement. The SiGe alloy layer provides stress-induced mobility improvement without requiring larger transistor sizes, allowing both reliability and productivity to be maintained simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased carrier mobility for both N-type and P-type transistors, allowing for more transistors to be fabricated per unit area without increasing planar size, while simplifying the fabrication process by reducing the number of steps required for forming fin-type structures.
Implementation Method 1
sequential etching processes to create fin-type structures with specific depths and liner formations, allowing for simultaneous patterning of NFET and PFET structures with different materials, thereby enhancing carrier mobility
Data Source
AI summary
A method of fabricating a semiconductor device is provided as follows. A channel layer is formed on a strain relaxed buffer (SRB) layer. A first etching process is performed on the channel layer and the SRB layer to form a plurality of trenches. The trenches penetrate through the channel layer and into the SRB layer to a first depth. First liners are formed on first sidewalls of the trenches having the first depth. The first liners cover the first sidewalls. A second etching process is performed on the SRB layer exposed through the trenches. The second etching process is performed on the SRB layer using a gas etchant having etch selectivity with respect to the first liners so that after the performing of the second etching process, the first liners remain on the first sidewalls.