Semiconductor Fin Smoothing for SiGe Channel Surface Uniformity
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Solution Overview
Problem
The scaling of multi-gate transistors in semiconductor devices leads to surface roughness and non-uniform composition on silicon germanium channels, resulting in reduced mobility and performance.
Innovation Solution
A self-limiting etch is used to clean the surface of silicon germanium channels, followed by a thin silicon deposition without air break, allowing intermixing to achieve a smooth Si70Ge30 surface and original fin width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are scaled down to increase device density, then device capacity increases, but surface roughness and non-uniform composition develop on silicon germanium channels
Solution Approach 1:
The patent changes the chemical parameters of the etch process by introducing a self-limiting etch step that selectively removes rough surfaces. The etch process is controlled to stop automatically when the desired smoothness is achieved, transforming the surface morphology parameter without requiring manual intervention or complex equipment
Solution Approach 2:
The self-limiting etch process is designed to automatically terminate when the surface is sufficiently smooth, using the surface itself as the limiting factor. The etch consumes the rough surface material and stops when the underlying smooth surface is exposed, making the process self-regulating without external control mechanisms
2Productivity
If multi-gate transistors are scaled down to increase device density, then device capacity increases, but mobility and performance are reduced
Solution Approach 1:
The patent performs surface cleaning and smoothing actions before subsequent processing steps. By removing surface roughness and non-uniform composition early in the fabrication sequence, the channel surface is prepared in advance to support high-mobility transistor operation at scaled dimensions
Solution Approach 2:
The patent replaces mechanical or physical surface treatment methods with a chemical etch process. Instead of using mechanical polishing or other physical smoothing techniques, a self-limiting chemical etch is employed to selectively remove rough surface material, achieving smoother results without mechanical contact
3Manufacturing precision
If a self-limiting etch is used to clean the surface, then surface smoothness improves, but fin width may change
Solution Approach 1:
The self-limiting etch process is designed to affect only the surface layer of the fin structure, leaving the bulk fin width unchanged. The etch selectively removes material from the rough surface region while stopping before penetrating into the main fin body, achieving local surface improvement without global dimensional change
Solution Approach 2:
The patent introduces a thin silicon deposition step as an intermediary between the etch process and subsequent high-k deposition. This intermediate silicon layer serves as a buffer that compensates for any minor width changes caused by the etch, ensuring the final fin dimensions remain accurate
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process provides a very smooth and clean surface for high-k deposition, enhancing mobility and overall performance of transistors.
Implementation Method 1
A self-limiting etch is used to clean the surface of silicon germanium channels
Implementation Method 2
followed by a thin silicon deposition without air break, allowing intermixing to achieve a smooth Si70Ge30 surface
Implementation Method 3
allowing intermixing to achieve a smooth Si70Ge30 surface
Data Source
AI summary
Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.