Semiconductor Fin Structures With Spacer-Defined Uniform Patterning
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Solution Overview
Problem
Conventional FinFET manufacturing processes face issues with pattern loading effects due to hard masks having pattern-dense and pattern-sparse regions, leading to variations in fin formation and affecting transistor performance.
Innovation Solution
A method is employed where semiconductor fins are patterned after their formation, using a sequence of deposition and etching steps to form spacers and mandrels, allowing for uniform patterning of fins and isolation regions, thereby mitigating the pattern loading effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If hard masks are used as etching masks to form fins, then the fin formation process is simplified, but pattern loading effects cause variations in fin dimensions between pattern-dense and pattern-sparse regions
Solution Approach 1:
The patent segments the fin formation process into multiple stages: first forming mandrels with initial hard masks, then forming spacers around mandrels, and finally using the spacers as etching masks to create fins. This segmentation allows the pattern loading effect to be avoided because the spacer thickness (which determines fin width) is controlled by conformal deposition rather than direct lithography, achieving both process feasibility and dimension uniformity.
Solution Approach 2:
The patent performs preliminary actions by first forming mandrels and then depositing conformal spacer layers around them before the actual fin etching. This preliminary spacer formation establishes a uniform fin width definition that is independent of the underlying hard mask pattern density, thereby pre-compensating for pattern loading effects before the critical fin formation step.
2Length of moving object
If fins are formed with smaller dimensions to meet down-scaling requirements, then transistor size is reduced, but process variations in fin formation become more pronounced
Solution Approach 1:
The patent transitions from defining fin width in the lateral lithography dimension to defining it through the vertical deposition dimension. The spacer thickness, controlled by atomic layer deposition or chemical vapor deposition, determines the fin width. This dimensional shift from 2D lithography to 3D conformal deposition provides better control precision for sub-20nm fin dimensions, reducing process variations.
3Quantity of substance
If the aspect ratio of gaps between fins is increased to accommodate thinner fins, then fin density is improved, but the formation process becomes more prone to variations
Solution Approach 1:
The spacer formation process is self-aligned and self-defining. The conformal deposition automatically conforms to the mandrel geometry, and the spacer thickness is determined by the deposition process parameters rather than lithographic resolution. This self-service mechanism inherently maintains uniformity even as fin dimensions scale down and gap aspect ratios increase, stabilizing the formation process.
Data Source
AI summary
A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region.