Semiconductor Fin Structure With Local Thickness Tuning for Logic and Memory
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving optimal performance in both logic and memory devices due to the limitations of fin field effect transistors (FinFETs), particularly in terms of current flow and short channel effects, as existing designs struggle to balance device density, performance, and cost.
Innovation Solution
The approach involves forming fin structures with varying thicknesses and compositions for logic and memory devices, where the top fin element of logic devices is thicker to enhance current flow and the final gate stack of memory devices provides better control over the channel to improve short channel effects, allowing for flexible performance tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the top fin element is made thicker to enhance on-current, then the performance of logic devices is improved, but the control over the channel deteriorates
Solution Approach 1:
The patent applies different fin thicknesses to different device types within the same semiconductor structure. Logic devices have thicker top fin elements to enhance on-current, while memory devices have thinner top fin elements that are fully encapsulated by the gate stack for better channel control. This local differentiation resolves the contradiction by optimizing each device type for its specific function rather than using a uniform design.
2Object-affected harmful factors
If the top fin element is encapsulated within the final gate stack to improve channel control, then short channel effects are reduced, but the on-current decreases
Solution Approach 1:
The patent implements different fin structures for different device regions: memory devices have top fin elements fully encapsulated by the gate stack to minimize short channel effects, while logic devices have thicker top fin elements extending beyond the gate stack to maximize on-current. This spatial differentiation allows each device type to optimize for its primary requirement.
Solution Approach 2:
The semiconductor structure is segmented into distinct logic device regions and memory device regions with different fin thickness characteristics. This segmentation allows independent optimization of fin structure for each device type, resolving the trade-off between channel control and on-current by applying the appropriate structure to the appropriate device segment.
3Ease of manufacture
If a uniform fin thickness is used across all devices, then manufacturing is simplified, but optimal performance for both logic and memory devices cannot be achieved
Solution Approach 1:
The patent forms a sacrificial layer with varying thicknesses in different regions before growing the semiconductor material. This preliminary action of creating a thickness profile in the sacrificial layer enables subsequent self-aligned etching processes to automatically produce the desired different fin thicknesses without requiring complex additional manufacturing steps, thus maintaining ease of manufacture while achieving optimal performance.
Data Source
AI summary
A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes forming a first trench and a second trench in a first semiconductor material. The first trench is deeper than the second trench. The method also includes forming a second semiconductor material in the first trench and the second trench, patterning a first portion of the second semiconductor material in the first trench and a first portion of the first semiconductor material below the first portion of the second semiconductor material into a first fin structure, and patterning a second portion of the second semiconductor material in the second trench and a second portion of the first semiconductor material below the second portion of the second semiconductor material into a second fin structure, and forming an isolation structure surrounding the first fin structure and the second fin structure.