Semiconductor Fine Interconnection via Spacer Oxidation

The patent divides the patterning process into multiple stages: first forming mandrels at a relaxed pitch, then using spacer deposition and selective removal to create the final fine-pitch pattern. This segmentation allows each stage to operate at optimal dimensions, achieving 40nm or smaller pitch with precise alignment by separating the pattern generation from the final feature definition.

The method performs preliminary actions by first forming the mandrel structure and spacers before final via hole formation. The spacers are deposited and patterned in advance to define the exact positions where via holes will later be formed, ensuring precise alignment is built into the structure before the actual via formation occurs.

The patent transitions from two-dimensional planar patterning to three-dimensional spacer-based patterning. By depositing conformal spacers on mandrels and using vertical sidewalls as alignment references, the method adds a dimensional element that enables precise lateral positioning independent of the original mandrel pitch, allowing high integration density with maintained alignment precision.

The spacer structures serve as self-aligned masks that automatically define the via hole positions based on their own geometry and deposition conformality. The spacers' sidewalls provide inherent alignment references that guide subsequent etching and via formation processes, eliminating the need for separate alignment operations and ensuring precision at reduced pitches.