Verifying Semiconductor Device Finger Counts in Layout Diagrams
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Previous methods for layout versus schematic (LVS) verification, such as those using Calibre, have not been able to effectively verify that the number of device fingers in a layout diagram corresponds to the number of device fingers in a corresponding schematic diagram, which is crucial for ensuring proper circuit performance, especially at sub-micron levels.
Innovation Solution
A computer system that determines a plurality of sub-circuits from a netlist, performs a two-phase checking process to verify that the number of device fingers in a layout diagram matches the number in a schematic diagram, by comparing total finger counts and checking finger parameters, and ensures accurate representation of device fingers within diffusion regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional LVS verification methods are used, then general layout versus schematic verification is performed, but device finger count verification is not achieved
Solution Approach 1:
The verification process is segmented into two distinct phases: Phase 1 extracts and compares device finger information from schematic diagrams, while Phase 2 extracts and compares the same information from layout diagrams. This segmentation allows each phase to specialize in verifying specific aspects of device representation, thereby achieving precise device finger count verification that conventional unified LVS methods cannot provide.
Solution Approach 2:
The system performs preliminary extraction of device finger information from both schematic and layout diagrams before performing the actual comparison. By pre-processing and organizing the finger count data from both representations, the system prepares the verification process in advance, enabling accurate matching and identification of discrepancies in device finger representation.
2Measurement precision
If detailed device finger verification is implemented, then verification accuracy is improved, but verification complexity increases
Solution Approach 1:
The complex verification task is divided into manageable segments: Phase 1 handles schematic diagram analysis and device finger extraction, while Phase 2 handles layout diagram analysis. Each phase focuses on specific verification objectives, reducing the perceived complexity while maintaining high verification accuracy for device finger representation.
Solution Approach 2:
The system introduces an intermediary comparison mechanism that bridges the schematic and layout representations. By using a standardized comparison framework that operates on extracted device finger parameters, the system simplifies the verification process while achieving detailed accuracy in device finger count and configuration verification.
Data Source
AI summary
A system for verifying that device fingers of a semiconductor circuit have been properly represented by a corresponding layout diagram. The system determines a plurality of sub-circuits, from within a netlist of a schematic diagram, to be verified. Each sub-circuit of the plurality of sub-circuits includes a multi-finger device. The system also determines a first number of fingers included in the plurality of sub-circuits as represented by the schematic diagram. The system also determines a second number of fingers included in the plurality of sub-circuits as represented by the corresponding layout diagram. The system compares the first number of fingers against the second number of fingers. The system reports an error if the first number of fingers does not correspond to the second number of fingers.