Semiconductor Finger Layout With Stacked Gate Wiring for Low Capacitance
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing size due to increased gate-source capacitance and larger dimensions resulting from gate wiring overlapping with source fingers.
Innovation Solution
The semiconductor device design includes a configuration where source and gate fingers are arranged to minimize overlap, with non-contact intersecting gate wirings, and utilizes vias to connect source fingers to metal layers, allowing for reduced gate resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate wiring overlaps with source fingers to connect gate fingers, then gate resistance is reduced, but gate-source capacitance increases and device size increases
Solution Approach 1:
The gate wiring is routed in a different spatial dimension (above or below the source fingers through stacked wiring layers) rather than overlapping in the same plane. This allows the gate wiring to connect gate fingers effectively while avoiding direct overlap with source fingers, thereby reducing gate-source capacitance while maintaining low gate resistance through the stacked connection path.
Solution Approach 2:
The gate wiring connection is segmented into multiple sections: portions that overlap with gate fingers (for low resistance connection) and portions that are separated from source fingers (for low capacitance). This segmentation allows different sections of the gate wiring to serve different functions optimally.
2Reliability
If gate wiring overlaps with source fingers to connect gate fingers, then gate resistance is reduced, but device size increases
Solution Approach 1:
By utilizing stacked wiring layers (different vertical dimensions), the gate wiring can be routed above or below the source fingers rather than requiring additional lateral space. This dimensional transition allows compact device layout while maintaining effective gate finger connections with low resistance.
Solution Approach 2:
The gate wiring structure serves multiple functions: it provides low-resistance electrical connection to gate fingers, maintains separation from source fingers to control device size, and integrates with the overall device architecture through the stacked layer configuration.
Data Source
AI summary
A semiconductor device includes a substrate, a first source finger provided on the substrate, a first gate finger provided adjacent to the first source finger in a width direction of the first source finger, a second source finger having a width smaller than a width of the first source finger, a second gate finger provided adjacent to the second source finger in the width direction of the second source finger, a first source wiring connecting the first source finger to the second source finger, a first gate wiring sandwiching the second source finger between the first gate wiring and the second gate finger, a second gate wiring intersecting the first source wiring in a non-contact manner, and connecting the first gate wiring to the first gate finger, and a first drain finger sandwiching the first gate finger and the second gate finger between the first drain finger.