Semiconductor Device With Vertical FinFET Memory Cell Design
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Solution Overview
Problem
The increasing miniaturization of MOS transistors in semiconductor integrated circuits leads to challenges in suppressing leak currents and maintaining operational stability due to hot carrier effects and reduced gate capacitance, resulting in soft-error phenomena in static memory cells.
Innovation Solution
A semiconductor device with a static memory cell design that includes six MOS transistors, featuring pillar-shaped semiconductor layers with gates formed on side walls, where the channel length of driver transistors is shorter than access transistors, and a method for fabricating these cells to ensure operational stability and prevent soft errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of MOS transistors is reduced to increase integration density, then the area of the circuit is reduced, but leak currents increase and operational stability deteriorates due to hot carrier effects
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional FinFET structures with vertical channels extending from the substrate surface. This dimensional change increases the effective channel area and gate control without increasing the planar footprint, thereby maintaining high integration density while improving current driving capability and reducing hot carrier effects through better electrostatic control
Solution Approach 2:
The patent implements a stacked memory cell architecture where multiple active regions and transistor structures are vertically nested within a single planar footprint. The FinFET structures are nested within isolation regions, and multiple storage nodes are stacked vertically, enabling higher integration density without compromising individual transistor performance
2Area of stationary object
If the gate capacitance is reduced due to miniaturization, then the area is reduced, but the ability to retain data deteriorates leading to soft-error phenomena
Solution Approach 1:
The patent modifies the physical and electrical parameters of the transistor structures, including increasing the effective channel width through vertical fins, optimizing doping concentrations in the FinFET regions, and adjusting gate lengths to maintain adequate gate capacitance. These parameter changes ensure sufficient charge storage capability in miniaturized cells while maintaining small area footprint
Solution Approach 2:
The patent employs composite material structures including high-k dielectric materials for gate insulation, metal gate electrodes, and doped semiconductor regions with optimized carrier concentrations. These composite structures enable enhanced charge retention capability through improved dielectric properties and controlled charge distribution, preventing soft errors in miniaturized memory cells
3Reliability
If two driver transistors are used to double the current driving force, then the operational stability is improved, but the memory cell area increases
Solution Approach 1:
The patent combines multiple transistor functions into single FinFET structures. The vertical FinFET design integrates the channel, gate, and source/drain regions in a compact three-dimensional configuration that provides enhanced current driving force equivalent to multiple planar transistors. The surrounding gate structure envelops the semiconductor fin from multiple sides, effectively multiplying the gate control and current capability within a single device footprint
Solution Approach 2:
By transitioning to vertical FinFET structures with channels extending perpendicular to the substrate, the patent achieves increased effective channel width and current driving force without increasing the planar area. The three-dimensional geometry allows multiple active channels to be stacked vertically within the same footprint, providing the equivalent current capability of multiple driver transistors while reducing overall cell area
Data Source
AI summary
A semiconductor memory device includes a static memory cell having six MOS transistors arranged on a substrate. The six MOS transistors include first and second NMOS access transistors, third and fourth NMOS driver transistors, and first and second PMOS load transistors. Each of the first and second NMOS access transistors has a first diffusion layer, a pillar-shaped semiconductor layer, and a second diffusion layer arranged vertically on the substrate in a hierarchical manner. Each of the third and fourth NMOS driver transistors has a third diffusion layer, a pillar-shaped semiconductor layer, and a fourth diffusion layer arranged vertically on the substrate in a hierarchical manner. The lengths between the upper ends of the third diffusion layers and the lower ends of the fourth diffusion layers are shorter than the lengths between the upper ends of the first diffusion layer and the lower ends of the second diffusion layers.