Semiconductor Device Flag Pad Delay Correction
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Solution Overview
Problem
In semiconductor memory devices with stacked chips, varying bonding wire lengths cause timing differences in signal output, leading to potential malfunctions due to mismatched delay values, which are typically addressed through additional manufacturing processes and different mask patterning for each chip, increasing costs and time.
Innovation Solution
The implementation of flag pads and internal circuits that adjust AC parameters like tDQSCK based on chip stack information, allowing for active correction of delay values across all stacked chips using the same mask patterning process, thereby minimizing area and manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If correction circuits are provided in stacked semiconductor chips to correct delay amounts, then AC parameter control is improved, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent extracts the delay correction function from complex correction circuits and implements it through a simplified flag pad mechanism. The flag pad, when connected to VDD through bonding wires of different lengths, automatically generates different voltage levels that select appropriate delay values in the DLL circuit, eliminating the need for complex correction circuits while maintaining AC parameter control capability.
Solution Approach 2:
The patent introduces flag pads as intermediary elements that mediate between the bonding wire length differences and the DLL delay adjustment. The flag pad serves as a simple interface that converts physical bonding wire length variations into electrical voltage signals, which then control the delay selection in the DLL circuit without requiring complex correction logic.
2Manufacturing precision
If fuse cutting processes are used to correct delay amounts, then AC parameter control is improved, but manufacturing time and costs increase
Solution Approach 1:
The patent implements delay correction values during the wafer fabrication stage itself, rather than requiring post-fabrication fuse cutting processes. The flag pad connections and voltage level selections are determined and embedded in the chip design before fabrication, allowing delay correction to be built-in during normal manufacturing without additional time-consuming steps.
Solution Approach 2:
The patent replaces the mechanical fuse cutting process with an electrical voltage-level-based delay selection mechanism. Instead of physically cutting fuses to disable correction circuits, the system uses different voltage levels on flag pads to electronically select appropriate delay values, eliminating the need for mechanical intervention and reducing manufacturing time.
3Manufacturing precision
If different mask patterning processes are used for chips with correction circuits, then AC parameter control is improved, but manufacturing costs and complexity increase
Solution Approach 1:
The patent makes the flag pad structure universal across all stacked semiconductor chips, regardless of their position in the stack. The same flag pad design and connection methodology can be applied to all chips, allowing them to be manufactured using identical mask patterning processes. This universal approach enables AC parameter control without requiring different manufacturing processes for different chip types.
Solution Approach 2:
The patent achieves homogeneity in manufacturing by using identical mask patterning processes for all stacked chips. The flag pad structure and its connection to VDD through bonding wires is implemented uniformly across all chips in the stack, ensuring that all chips can be manufactured through the same process without requiring special handling or different patterning for chips with correction functionality.
4Productivity
If bonding wires of different lengths are used for stacked chips, then chip stacking is enabled, but timing differences in signal output occur
Solution Approach 1:
The patent changes the electrical parameter (voltage level) on the flag pads based on the bonding wire length. Chips with longer bonding wires have their flag pads connected to VDD, generating a high voltage level that selects a larger delay value in the DLL circuit. This parameter change compensates for the longer signal transmission time through the bonding wire, maintaining synchronized output timing across all stacked chips.
Data Source
AI summary
A semiconductor device includes a package substrate having a plurality of external connection terminals disposed on a first surface thereof and a plurality of internal connection terminals disposed on a second surface thereof and electrically connected with corresponding one of the external connection terminals, a first semiconductor chip stacked over the second surface of the package substrate and having a first flag pad for providing first information and a first internal circuit for adjusting a parameter by a first correction value in response to the first information provided from the first flag pad, and a second semiconductor chip stacked over the first semiconductor chip and having a second flag pad for providing second information and a second internal circuit for adjusting the parameter by a second correction value in response to the second information provided from the second flag pad.