Semiconductor Insulation Film Layout for Flat Termination Regions
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Solution Overview
Problem
Forming a flat structure in semiconductor devices like IGBTs using CMP is challenging due to structural differences between the cell and termination regions.
Innovation Solution
A semiconductor device manufacturing method involving the formation of a semiconductor layer of a first conductivity type on a protrusion portion, with specific insulation film thickness variations and controlled etching processes to form openings and projections, allowing for a flat structure without CMP.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If CMP (chemical mechanical polishing) is used to form a flat structure, then surface flatness is improved, but manufacturing cost increases and process complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the insulation film with controlled thickness variations before subsequent etching processes. The film is deposited with intentionally designed thickness gradients that will compensate for structural differences between cell and termination regions during processing, enabling flat surface formation without CMP polishing.
Solution Approach 2:
The patent changes the thickness parameter of the insulation film across different regions. By controlling the film thickness to be non-uniform (thinner in cell region, thicker in termination region), the process compensates for underlying structural differences and achieves surface flatness through subsequent etching rather than mechanical polishing.
2Object-generated harmful factors
If insulation film thickness is increased in termination region, then side etching is reduced, but film deposition complexity increases
Solution Approach 1:
The patent applies local quality by creating spatially varying insulation film thickness across different device regions. The film thickness is locally optimized: thinner in the cell region and thicker in the termination region, allowing each region to have the specific properties needed for its function while controlling side etching in the termination region.
Solution Approach 2:
The patent solves the side etching problem by transitioning from a uniform 2D film approach to a 3D thickness variation approach. By controlling film thickness in the vertical dimension across different horizontal regions, the process prevents side etching without requiring complex deposition techniques.
3Manufacturing precision
If conventional etching is used on protrusion portions, then guard ring widens, but device performance deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-forming the insulation film with specific thickness characteristics before the etching process. This preliminary film structure prevents excessive side etching during subsequent processing, thereby preventing guard ring widening and maintaining device performance without requiring additional corrective steps.
Data Source
AI summary
A semiconductor device manufacturing method according to this embodiment includes forming a first insulation film, on a first face of a semiconductor substrate, such that a film thickness of the first insulation film at a step portion of a protrusion portion provided in a first region of the first face is thinner than a film thickness of the first insulation film at an upper surface of the protrusion portion or a film thickness of the first insulation film at a second region of the first face, the second region different from the first region. The manufacturing method includes removing part of the first insulation film using a mask material as a mask to form an opening portion of the first insulation film and a projection portion of the first insulation film. The manufacturing method includes removing the second insulation film together with part of the projection portion.