Semiconductor Device Flip-Chip Bonding Parasitic Inductance
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Solution Overview
Problem
Conventional semiconductor devices face challenges in achieving high-speed, high-packaging density, and low-cost integration of multiple chips due to increased parasitic inductance and capacitance from wire bonding and the complexity of forming additional wiring lines and bumps, which complicates manufacturing and increases costs.
Innovation Solution
A semiconductor device design featuring a wiring chip with parallel connection pads and semiconductor chips mounted via flip-chip bonding, reducing inductance and allowing for high-speed operation while maintaining low manufacturing costs by using a stable process and shared silicon substrates for increased reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If wire bonding is used to connect chips, then chip mounting is achieved, but parasitic inductance and capacitance increase making high-speed applications difficult
Solution Approach 1:
The patent extracts and eliminates the wire bonding process entirely by using direct bump bonding between chips. The connection is achieved through metal bumps formed directly on the chip pads, removing the intermediate wire structure that causes parasitic inductance and capacitance, thereby enabling high-speed operation.
Solution Approach 2:
The patent replaces the mechanical wire bonding system with a direct metal-to-metal bump bonding system. This substitution eliminates the long wire connections and their associated parasitic elements, providing a more efficient electrical connection suitable for high-speed applications.
2Ease of manufacture
If additional wiring lines and bumps are formed on chips, then chip mounting is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies preliminary action by forming the metal bumps on chip pads during the semiconductor manufacturing process itself, before chip mounting. This integrates the bump formation into the standard fabrication flow, eliminating the need for separate post-manufacturing steps and reducing overall manufacturing complexity.
Solution Approach 2:
The patent merges the bump formation process with the existing semiconductor manufacturing process. The metal bumps are formed as part of the standard chip fabrication sequence, combining multiple functions into a unified manufacturing flow and avoiding additional complex steps.
3Area of stationary object
If chips are mounted with high packaging density, then space utilization improves, but wiring length reduction becomes challenging
Solution Approach 1:
The patent transitions from planar wire bonding to three-dimensional bump bonding, allowing vertical connections between chips. This dimensional change enables high packaging density while maintaining short effective wiring lengths, as signals can travel vertically through bumps rather than laterally through wires across the chip surface.
Solution Approach 2:
The patent removes the wire bonding infrastructure entirely, replacing it with direct bump connections. This extraction of the wire layer simplifies the interconnection structure and allows for more compact chip arrangements without the space requirements and parasitic effects associated with traditional wire bonds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables high-speed, high-density chip mounting with reduced manufacturing costs and improved reliability by minimizing wiring lengths and using flip-chip bonding to decrease inductance and prevent crosstalk, while allowing for efficient signal input/output and power supply.
Implementation Method 1
bumps made of solder, gold or copper are formed and compression-bonded to a substrate
Data Source
AI summary
The present invention provides a semiconductor device which can realize the mounting of a plurality of chips at a high-speed, with high packaging density and at a low cost. In mounting a memory device chip 103 and an ASIC 104 on a wiring chip 102, connection pads 110, 116 are respectively formed along one opposing sides of the memory device chip 103 and the ASIC 104 on the wiring chip 102, the arrangement positions of the respective connection pads 110, 116 define the shortest distance assumes the shortest distance therebetween and, at the same time wiring lines which are formed on the wiring chip 102 are also shortened. Accordingly, it is possible to mount the memory device chip 103 and the ASIC 104 on the wiring chip 102 with high packaging density and, at the same time, since the wiring distance can be shortened, the high speed operation can be realized.