Self-Aligned Floating Gate Formation in Semiconductor Memory
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Solution Overview
Problem
Conventional methods for forming semiconductor memory devices require multiple lithography steps to define floating and control gates, leading to increased complexity, cost, and alignment challenges as feature sizes shrink, necessitating a more precise and simplified process.
Innovation Solution
A self-aligned method is developed to form a semiconductor structure by integrating the floating gate definition with active area and gate contact patterning steps, using a mask layer to adjust the floating gate area and reduce lithography processes, involving the formation of dielectric isolations, conductive layers, and conformal layers to enhance coupling ratios without additional photomasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional methods use multiple lithography steps to define floating gate and control gate patterns, then the coupling area between gates can be adjusted, but the process complexity increases and alignment precision becomes difficult to control
Solution Approach 1:
The patent combines the definition of floating gate pattern and control gate pattern into a single lithography step. The method uses a first photoresist layer to define the active area and floating gate pattern, then uses the same patterned photoresist layer as a mask during subsequent processing to define the control gate pattern, eliminating the need for separate lithography steps and improving alignment precision.
Solution Approach 2:
The patterned photoresist layer serves multiple functions: it defines the floating gate pattern, acts as a mask for forming the control gate pattern, and guides the formation of dielectric layers. This self-aligned approach allows the structure to define its own patterns without requiring additional external alignment processes.
2Manufacturing precision
If additional photomask procedures are implemented to increase coupling area, then the coupling ratio improves, but the cost and process time increase
Solution Approach 1:
The patent merges the formation of floating gate and control gate patterns into a single lithography process, eliminating multiple photomask procedures. The coupled gate structure is formed using the same photoresist pattern, which simultaneously defines both gates and their relative positioning, thereby maintaining high coupling ratio while reducing process time.
Solution Approach 2:
The method performs preliminary patterning of the photoresist layer to define the active area and floating gate pattern before forming the control gate. This preliminary pattern serves as a self-aligned mask that pre-determines the precise location and dimensions of the control gate, ensuring optimal coupling without requiring additional alignment steps.
3Area of moving object
If feature size shrinks to improve device integration, then device density increases, but alignment precision becomes more difficult to control
Solution Approach 1:
The self-aligned method uses the photoresist pattern itself as the alignment reference for subsequent processing steps. The patterned photoresist layer defines the floating gate and simultaneously serves as the mask for forming the control gate, eliminating the need for separate alignment operations that would be particularly problematic at reduced feature sizes.
Solution Approach 2:
By combining the definition of multiple gate patterns into a single lithography step, the patent eliminates cumulative alignment errors that would otherwise accumulate with each additional lithography step. This is particularly beneficial for scaled devices where alignment tolerance is reduced.
Data Source
AI summary
A method of forming a semiconductor structure is provided. The method includes providing a substrate and forming a mask layer on the substrate, Next, dielectric isolations are formed in the mask layer and the substrate, wherein the dielectric isolations extend above the substrate. Then, the mask layer is removed to expose a portion of the substrate, and a dielectric layer is formed on the exposed portion of the substrate. Subsequently, a first conductive layer is formed on the dielectric layer, and a portion of the dielectric isolation is removed, wherein a top surface of the remaining dielectric isolation is lower than a top surface of the first conductive layer. Moreover, a conformal layer is formed over the substrate, and a second conductive layer is formed on the conformal layer.