Semiconductor Device Floating Potential Region

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Solution Overview

Problem

The challenge is to reduce chip size in semiconductor devices while integrating high voltage startup and high side circuits on the same chip, as they operate with different high-voltage behaviors, requiring separate voltage blocking structures and isolated regions, which hinders chip shrinkage.

Innovation Solution

A semiconductor device design featuring a semiconductor base body with specific conductivity type regions, isolation regions, and a floating potential region, allowing the startup element and high side circuit to share voltage blocking areas and maintain independent high voltage behaviors, achieved through a configuration with double or triple isolation regions and metal wiring connections to floating potential regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If startup element and high side circuit are arranged in separate regions isolated by ground potential region, then high voltage behaviors are independently maintained, but chip size cannot be reduced

Engineering Contradiction:

Improvehigh voltage behavior independenceVSAvoidchip size

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

A floating potential region is introduced as an intermediary between the startup element and high side circuit. This floating potential region acts as a mediator that allows both circuits to share common voltage blocking areas while maintaining electrical independence, thereby reducing chip size without compromising high voltage behavior independence

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent merges the voltage blocking areas of the startup element and high side circuit into a shared structure. By combining these previously separate blocking regions and using the floating potential region to maintain independence, the overall chip area is reduced while functional independence is preserved

Inventive Principle:

Principle #5Merging (Combining)

2Area of stationary object

If startup element and high side circuit share voltage blocking areas, then chip size is reduced, but parasitic npn bipolar transistor operation may occur

Engineering Contradiction:

Improvechip sizeVSAvoidparasitic npn bipolar transistor operation

Core Design Contradiction:

Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

The floating potential region serves as an intermediary that electrically isolates the startup element and high side circuit even when they share physical space and voltage blocking areas. This prevents the formation of parasitic npn bipolar transistor paths while allowing compact integration

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the electrical paths between the startup element and high side circuit through the floating potential region. This segmentation breaks potential parasitic current paths that would otherwise form npn bipolar transistor structures, enabling safe sharing of voltage blocking areas

Inventive Principle:

Principle #1Segmentation

3Reliability

If double or triple isolation regions are implemented, then noise resistance and thermal stability are improved, but manufacturing complexity increases

Engineering Contradiction:

Improvenoise resistance and thermal stabilityVSAvoidmanufacturing complexity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The floating potential region performs multiple functions simultaneously: it provides electrical isolation to prevent parasitic transistor operation, establishes proper biasing for the shared voltage blocking areas, and maintains high voltage independence. This multi-functionality reduces the need for additional complex isolation structures

Inventive Principle:

Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enables significant reduction in chip size while maintaining breakdown voltage and noise resistance, suppressing parasitic npn bipolar transistor operation and preventing thermal runaway, thus achieving a high voltage chip with improved noise resistance and cost-effectiveness.

Implementation Method 1

a first region of a first conductivity type selectively provided in an upper part of the semiconductor base body; a second region of a second conductivity type provided in contact with the first region

Methodology Applied

Scientific Effectpn junction voltage blocking: Electric Field

Implementation Method 2

a first isolation region provided between the second region and the fourth region; and a second isolation region provided between the third region and the fourth region

Methodology Applied

Scientific EffectElectrical isolation: Electrical Resistance

Data Source

PatentUS20230187437A1Semiconductor device

Publication Date: 2023.06.15 FUJI ELECTRIC CO LTD

AI summary

A semiconductor device includes: a semiconductor base body; a first region of a first conductivity type selectively provided in an upper part of the semiconductor base body; a second region of a second conductivity type provided in contact with the first region in the upper part of the semiconductor base body; a third region of the second conductivity type provided away from the second region in the upper part of the semiconductor base body; a fourth region of the second conductivity type provided between the second region and the third region in the upper part of the semiconductor base body; a first isolation region provided between the second region and the fourth region; and a second isolation region provided between the third region and the fourth region.