Semiconductor Structure Floating Wells for ESD Trigger Voltage Reduction
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Solution Overview
Problem
Typical semiconductor controlled rectifiers (SCRs) have high trigger voltages for electrostatic discharge (ESD) protection, leading to inefficient ESD protection due to avalanche breakdown at the N/P junction before activation, necessitating improved ESD protection mechanisms.
Innovation Solution
A semiconductor structure comprising a first and second well, heavily doped regions, and a switch that floats the wells during ESD events to introduce a displacement current, reducing the trigger voltage and preventing latch-up, while maintaining normal operation by coupling the wells to nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a typical SCR is used for ESD protection, then the structure provides basic ESD protection capability, but the trigger voltage is too high due to avalanche breakdown at the N/P junction before SCR activation
Solution Approach 1:
The patent applies preliminary action by pre-configuring the wells in a floating state before ESD events occur. The switch is positioned to automatically float the wells when ESD conditions are detected, preparing the structure in advance to achieve lower trigger voltage and prevent avalanche breakdown before SCR activation.
Solution Approach 2:
The patent implements dynamics by making the well configuration changeable through the switch mechanism. The wells can dynamically transition between connected and floating states, allowing the structure to adapt its electrical characteristics based on operating conditions. This dynamic control enables optimization of trigger voltage for ESD protection while maintaining normal operation.
2Reliability
If the wells are floated to reduce trigger voltage, then ESD protection efficiency is enhanced, but the structure may become unstable during normal operation
Solution Approach 1:
The switch enables dynamic control of the well configuration, allowing the system to transition between floating state (for ESD protection with lower trigger voltage) and connected state (for stable normal operation). This dynamic adaptability resolves the contradiction by providing both ESD efficiency and operational stability as needed.
Solution Approach 2:
The patent changes the electrical state parameter of the wells by controlling their connection status through the switch. By changing from connected to floating state, the trigger voltage parameter is reduced for better ESD protection. The switch ensures this parameter change occurs only under appropriate conditions, maintaining stability during normal operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The floating well configuration lowers the trigger voltage for SCR activation, enhancing ESD protection efficiency and preventing latch-up, thereby improving the semiconductor structure's ability to handle electrostatic discharges effectively.
Implementation Method 1
floats the wells during ESD events to introduce a displacement current, reducing the trigger voltage
Implementation Method 2
an avalanche breakdown occurs at the N/P junction before the SCR is turned on
Data Source
AI summary
A semiconductor structure includes a first heavily doped region, a first well, a second well and a second heavily doped region disposed sequentially. The first well and the second heavily doped region have a first conductive type. The second well and the first heavily doped region have a second conductive type. The semiconductor structure further includes at least one switch, such that at least one of conditions (A) and (B) is satisfied. (A) The switch is coupled between the first well and the first node such that the first well is controlled by the switch and floated under an ESD protection mode. (B) The switch is coupled between the second well and the second node such that the second well is controlled by the switch and floated under an ESD protection mode.