Semiconductor Floor Plan Optimization via Power Model Selection
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Solution Overview
Problem
The process of designing semiconductor devices often results in suboptimal floor plans due to reliance on experience, leading to inadequate power characteristics, as the existing methods do not efficiently generate and select power models that satisfy system requirements.
Innovation Solution
A computer system-based method for semiconductor design simulation that generates multiple floor plans, power models, and selects one that satisfies system requirements by placing circuit blocks differently and analyzing power bump and ball models to optimize power characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If floor plans are decided based on experience, then the design process is simple, but the power characteristics are suboptimal
Solution Approach 1:
The system performs preliminary generation of multiple floor plans and their corresponding power models before final selection. By pre-generating various design options and evaluating their power characteristics in advance, the system identifies optimal configurations that satisfy power requirements while maintaining design efficiency through automated comparison and selection.
2Reliability
If multiple floor plans are generated and analyzed, then power characteristics are improved, but the design complexity increases
Solution Approach 1:
The system creates simplified power models that replicate the essential power characteristics of each floor plan without requiring full-scale detailed analysis. These power models serve as simplified representations that capture the key power consumption and distribution features, enabling efficient comparison and selection of optimal floor plans while reducing the computational complexity of the design process.
3Reliability
If power models are extracted and tested repeatedly, then system requirements are satisfied, but the design time increases
Solution Approach 1:
The system performs partial analysis by generating power models for multiple floor plans simultaneously and evaluating them against system requirements in parallel. Rather than iteratively refining a single floor plan through repeated extraction and testing, the method extracts power models for several candidate floor plans at once, performs comparative evaluation, and selects the optimal configuration that satisfies power requirements, thereby reducing total design time while ensuring requirement compliance.
Data Source
AI summary
Disclosed is a method implemented with a computer system executing instructions for a semiconductor design simulation. The method includes generating a plurality of floor plans placing a plurality of circuit blocks differently, generating a plurality of power models from the plurality of floor plans, and selecting a layout corresponding to one of the plurality of floor plans by selecting at least one power model satisfying system requirements from among the plurality of power models.