Semiconductor Device Fluorine Diffusion Layer NBTI Suppression
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for producing semiconductor devices introduce variations in the channel region and extension diffusion layer during miniaturization, leading to NBTI degradation, and lack effective control over the fluorine ion diffusion profile for improving reliability.
Innovation Solution
A semiconductor device structure with a fluorine diffusion layer having a profile that overlaps under the gate electrode, formed through a specific ion implantation and heat treatment process, is used to suppress NBTI degradation without introducing characteristics variations, and this structure is applicable to both p-channel and n-channel transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional heat treatment methods are used during miniaturization, then manufacturing process is simplified, but characteristics variations are introduced in the channel region and extension diffusion layer
Solution Approach 1:
The heat treatment process is segmented into two distinct stages: a first heat treatment at a higher temperature for a shorter duration to activate impurities and reduce substrate damage, and a second heat treatment at a lower temperature for a longer duration to achieve fluorine ion diffusion. This segmentation allows each stage to be optimized independently, preventing characteristics variations while maintaining process simplicity.
Solution Approach 2:
The first heat treatment is performed as a preliminary action before the second heat treatment. This preliminary heat treatment activates the implanted impurities and reduces interstitial silicon atoms, preparing the substrate for the subsequent fluorine ion diffusion process. This preliminary action prevents damage to the channel region and extension diffusion layer that would otherwise occur during miniaturization.
2Reliability
If fluorine ion implantation is performed to suppress NBTI degradation, then reliability is improved, but diffusion profile control becomes difficult
Solution Approach 1:
The diffusion profile of fluorine ions is controlled by changing the temperature parameter during the heat treatment process. The second heat treatment is performed at a lower temperature than the first heat treatment, but for a longer duration. This parameter change allows precise control over the diffusion depth and concentration profile of fluorine ions, ensuring they reach the appropriate region to suppress NBTI degradation without affecting other device characteristics.
Solution Approach 2:
The fluorine ion diffusion is localized to specific regions of the semiconductor substrate. By performing the second heat treatment at a lower temperature for a longer duration, fluorine ions diffuse preferentially into the channel region and extension diffusion layer where they are needed to suppress NBTI degradation, while maintaining different impurity concentrations in different regions of the device.
3Speed
If gate oxide film is made thinner to increase operating speed and reduce power consumption, then device performance is improved, but NBTI degradation reliability problems are highlighted
Solution Approach 1:
Fluorine ions are implanted and diffused into the channel region and extension diffusion layer as a preliminary anti-action against NBTI degradation. The fluorine atoms bond with silicon atoms in the substrate, creating a protective layer that prevents the formation of interface traps and oxide charges that cause NBTI degradation. This preliminary protective action allows the gate oxide film to be made thinner for improved performance without suffering from reliability problems.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described structure effectively suppresses NBTI degradation in both internal and peripheral transistors by ensuring the fluorine diffusion layer overlaps appropriately under the gate electrodes, enhancing the reliability and consistency of the semiconductor device.
Implementation Method 1
ions of an n-type impurity are implanted into the NMOS formation region 1b to form an extension diffusion layer 6. Then, in the presence of the photoresist 5, ions of a p-type impurity are implanted into the NMOS formation region 1b to form a pocket layer 7
Implementation Method 2
The second heat treatment is performed for the purpose of achieving the diffusion of the fluorine ion implantation region 9a
Implementation Method 3
The first heat treatment is performed for the purpose of sufficiently activating impurities while reducing the damage to the semiconductor substrate, and is performed at a high temperature for a short period of time by using a method such as RTA
Data Source
AI summary
A semiconductor device, including a first MIS-type transistor formed in a first region of a semiconductor region, the first region being of a first conductivity type, the first MIS-type transistor including: a first gate insulating film formed on the first region; a first gate electrode formed on the first gate insulating film; a first extension diffusion layer of a second conductivity type formed in a region of the first region under and beside the first gate electrode; and a first fluorine diffusion layer formed in a first channel region of the first conductivity type sandwiched between portions of the first extension diffusion layer, wherein portions of the first fluorine diffusion layer extend from the first extension diffusion layer and overlap together in a region directly under the first gate electrode.