Semiconductor Package Foil Positioning Pattern
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Solution Overview
Problem
Current semiconductor packaging methods face challenges in achieving high accuracy and low cost positioning of semiconductor devices on substrates, particularly in optical semiconductor packages, due to difficulties in using instruments like component placement systems and forming capture marks or positioning holes, which increase production time and costs.
Innovation Solution
A semiconductor package with a foil positioning pattern on the substrate that aligns with straight line portions of the semiconductor device, allowing for accurate positioning without the need for complex instruments or high-accuracy hole formation, using a process similar to foil wiring pattern formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a component placement system with camera-based positioning is used to detect and correct misalignment, then positioning accuracy is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent replaces expensive, complex instrumentation with simple, inexpensive positioning marks that can be formed using standard PCB fabrication processes. The positioning marks serve as disposable reference features that enable accurate alignment without requiring sophisticated detection equipment.
Solution Approach 2:
The patent substitutes the mechanical/optical measurement system (camera-based component placement system) with a geometric reference system (positioning marks). Instead of using active sensing and correction mechanisms, the solution uses passive geometric references that guide positioning through their physical configuration.
2Manufacturing precision
If positioning holes or notches are formed with high accuracy to engage with positioning jig, then positioning accuracy is improved, but manufacturing time and cost increase
Solution Approach 1:
The patent combines the positioning mark formation with the existing wiring pattern formation process. Both are created using the same photolithography and etching steps on the PCB substrate, eliminating the need for separate high-precision positioning hole formation operations.
Solution Approach 2:
The patent changes the approach from forming precise mechanical features (holes/notches) to forming planar geometric references (positioning marks). This parameter change allows positioning to be achieved through geometric alignment rather than mechanical engagement, reducing manufacturing complexity and time.
3Ease of manufacture
If capture marks are formed in regions that do not overlap with photodiode array, then positioning can be performed, but positioning accuracy is reduced
Solution Approach 1:
The patent extends the positioning reference from one-dimensional edge alignment to two-dimensional geometric patterns. The positioning marks provide multiple reference points and geometric constraints that enable accurate positioning without overlapping the photodiode array region.
Solution Approach 2:
The positioning marks are formed during the preliminary PCB fabrication process, before the semiconductor device is mounted. This allows the positioning references to be established in advance with high precision using standard PCB manufacturing techniques.
Data Source
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AI summary
A semiconductor package includes a semiconductor device and a substrate, the semiconductor device including a straight line portion on an outer periphery and the substrate supporting the semiconductor device. A foil positioning pattern is formed on a front surface of the substrate, the positioning pattern touching the straight line portion of the semiconductor device to regulate a position of the semiconductor device.