Semiconductor Device Forbidden Region Stress Management
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Solution Overview
Problem
The scaling down of semiconductor chips and increased integration lead to stress issues during bonding, which can impair the characteristics of semiconductor elements like MIS transistors when disposed under electrode pads, causing cracks in interlayer dielectrics and deteriorating transistor performance.
Innovation Solution
A semiconductor device design that includes a forbidden region in specific areas around the electrode pad and bump, where the connection between conductive layers is not formed, thereby preventing stress and cracks, allowing for reliable element placement under the pad without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the semiconductor element is disposed under the electrode pad to increase integration, then the degree of integration is improved, but stress during bonding impairs the characteristics of the semiconductor element
Solution Approach 1:
The patent applies local quality by creating a forbidden region with specific structural characteristics in the interlayer dielectric layer. This region has different properties (increased thickness or reinforced structure) compared to other areas, specifically designed to withstand bonding stress and protect the semiconductor element disposed underneath the electrode pad.
Solution Approach 2:
The patent implements beforehand cushioning by pre-forming a protective structure in the interlayer dielectric layer at the location where bonding stress will occur. This protective structure acts as a cushion that absorbs or distributes the stress during the bonding process, preventing damage to the semiconductor element before the stress is applied.
2Reliability
If the pad formation region and semiconductor element formation region are separately provided, then the characteristics of the semiconductor element are maintained, but the degree of integration is reduced
Solution Approach 1:
The patent applies segmentation by dividing the electrode pad structure into multiple layers, with the interlayer dielectric layer containing a specialized forbidden region segment that provides protection. This segmentation allows the pad region and element region to overlap spatially while maintaining functional independence and protection through the structured dielectric layer.
3Ease of manufacture
If the connection section is provided in the specific range outward from the electrode pad edge, then the conductive connection is achieved, but cracks occur in the interlayer dielectric due to stress
Solution Approach 1:
The patent applies taking out by extracting the connection function from the stress-prone forbidden region. The conductive layers are configured to connect to the electrode pad through pathways that bypass the forbidden region, removing the vulnerable connection section from the area where bonding stress causes cracking.
Solution Approach 2:
The patent uses an intermediary approach by introducing the forbidden region as a mediator between the electrode pad and the conductive layers. This intermediary structure manages the stress distribution, allowing conductive connections to be made without directly transmitting bonding stress through the connection sections.
Data Source
AI summary
A semiconductor device, including: a semiconductor layer having an active region; a first conductive layer formed above the semiconductor layer and having a first width; a second conductive layer connected to the first conductive layer and having a second width smaller than the first width; an interlayer dielectric formed above the semiconductor layer; an electrode pad formed above the interlayer dielectric and covering the active region when viewed from a top side; and a forbidden region provided in the semiconductor layer in a specific range positioned outward from a line extending vertically downward from an edge of at least part of the electrode pad. A connection section at which the first conductive layer and the second conductive layer are connected is not provided in the forbidden region.