Semiconductor Frame for Stable 3D NAND Pillar Etching
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Solution Overview
Problem
There is a demand for manufacturing technology that can stably form high-aspect-ratio holes for semiconductor pillars in three-dimensionally arranged NAND memory devices, which is challenging due to issues like charge buildup and arc discharge during the etching process.
Innovation Solution
The solution involves a memory device design with a semiconductor layer that includes a frame portion extending over the substrate and a link portion to neutralize charges, preventing arc discharge and ensuring stable formation of semiconductor pillars by using a semiconductor layer with a frame-shaped configuration and link portions to connect the source line and selection gates, thereby suppressing charge buildup.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional etching processes are used to form high-aspect-ratio holes for semiconductor pillars, then the memory capacity can be increased through three-dimensional arrangement, but charge buildup and arc discharge occur during the etching process, causing manufacturing instability
Solution Approach 1:
A semiconductor layer is introduced as an intermediary component between the substrate and the memory cell array. This semiconductor layer includes a frame portion that extends over the substrate and link portions that electrically connect the source line and selection gate, serving as a charge neutralization path that prevents charge buildup and arc discharge during etching processes
Solution Approach 2:
The invention converts the harmful effect of charge buildup during etching into a beneficial outcome by providing a controlled path for charge dissipation through the semiconductor layer. The frame portion and link portions create a deliberate charge neutralization mechanism that transforms the potential harm of charge accumulation into a stable manufacturing process
2Quantity of substance
If high-aspect-ratio holes are formed for three-dimensional memory structure, then memory capacity increases, but arc discharge damages the drive circuit during etching
Solution Approach 1:
The semiconductor layer acts as a protective intermediary between the etching process and the drive circuit. The frame portion extending over the substrate and the link portions create a shield that intercepts and neutralizes charges before they can accumulate and cause arc discharge that would damage the drive circuit
Solution Approach 2:
The semiconductor layer is formed in advance before the etching process to provide a protective cushioning effect. The frame portion and link portions are pre-configured to neutralize charges that will be generated during subsequent etching operations, preventing arc discharge damage before it can occur
Data Source
AI summary
A memory device includes a first conductive layer; a second conductive layer provided above the first conductive layer; a plurality of electrode layers stacked above the second conductive layer; a semiconductor pillar extending through the plurality of electrode layers and the second conductive layer, and connected to the first conductive layer; and a third conductive layer provided above the first conductive layer. The third conductive layer is positioned at a level substantially same as a level of the second conductive layer in an extension direction of the semiconductor pillar, and is made of a material same as a material of the second conductive layer. The third conductive layer is electrically isolated from the second conductive layer, and is electrically connected to the first conductive layer.