Semiconductor Package Frame Embedding with Redistribution Layer
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Solution Overview
Problem
The existing semiconductor packaging technologies, such as fan-in and fan-out packages, face challenges in efficiently mounting semiconductor chips on printed circuit boards due to size and spacing mismatches between chip connection pads and board mounting pads, limiting their application and requiring additional interposer substrates for mounting, which increases thickness and complexity.
Innovation Solution
A semiconductor package design featuring a frame with a recessed structure, a redistribution layer, and separate encapsulation of the semiconductor chip and passive components, allowing for direct mounting on a mainboard without an interposer substrate, with a redistribution layer connecting chip pads to the board wiring, and a shielding metal layer for EMI protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fan-in or fan-out packaging technology is used, then semiconductor chips can be mounted on printed circuit boards, but size and spacing mismatches between chip connection pads and board mounting pads occur, requiring additional interposer substrates that increase thickness and complexity
Solution Approach 1:
The patent introduces a redistribution layer as an intermediary structure between the semiconductor chip connection pads and the board mounting pads. This redistribution layer, disposed on the encapsulant surface, contains conductive patterns that perform electrical connection and signal redistribution, eliminating the need for separate interposer substrates while maintaining reliable electrical connections.
Solution Approach 2:
The patent transitions from planar pad-to-pad connection to a three-dimensional connection architecture. The redistribution layer is disposed on the encapsulant surface at a different vertical level, creating a fan-out effect where connection pads are redistributed to larger mounting areas. This dimensional transition allows direct mounting on mainboards without increasing package thickness through additional interposer layers.
2Adaptability or versatility
If interposer substrates are added for mounting, then size mismatch is resolved, but package thickness and complexity increase
Solution Approach 1:
The patent merges the functions of the encapsulant and the redistribution substrate into a single integrated structure. The redistribution layer is formed directly on the encapsulant surface, combining the protective encapsulation function with the electrical redistribution function. This integration eliminates the need for separate interposer substrates, reducing package thickness while maintaining mounting adaptability.
Solution Approach 2:
The encapsulant in this patent serves multiple functions: it provides mechanical protection for the semiconductor chip, acts as an insulating substrate, and serves as the base for the redistribution layer. This multi-functionality eliminates the need for dedicated interposer substrates, reducing overall package thickness while maintaining versatile mounting capabilities.
3Area of stationary object
If package size is reduced for mobile devices, then space is saved, but thermal and electrical characteristics may deteriorate
Solution Approach 1:
The patent employs a thin-film redistribution layer structure disposed on the encapsulant surface. This thin-film approach allows electrical redistribution and thermal management within a minimal thickness profile, enabling compact package design while maintaining effective thermal pathways from the semiconductor chip through the encapsulant to the board mounting interface.
Solution Approach 2:
The encapsulant and redistribution layer form a composite structure that combines the protective and insulating properties of the encapsulant with the conductive properties of the redistribution layer. This composite architecture enables efficient thermal management and electrical performance within a reduced package footprint suitable for mobile devices.
Data Source
AI summary
A semiconductor package includes a frame having a wiring structure and having a recess portion, a semiconductor chip having an active surface with a connection pad disposed thereon and disposed in the recess portion, an encapsulant sealing the semiconductor chip, and a redistribution layer having a first via connected to the connection and a second via connected to a portion of the wiring structure. The semiconductor chip includes a protective insulating film disposed on the active surface and having an opening exposing a region of the connection pad, and a redistribution capping layer connected to the region of the connection pad and extending onto the protective insulating film, and a surface of the redistribution capping layer is substantially the same level as a surface of the portion of the wiring structure, exposed from the first surface.


