Semiconductor Fuse Array Control Circuit Timing
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Solution Overview
Problem
Conventional semiconductor devices face challenges in controlling the read and precharge operations of fuse arrays, leading to increased drain-source voltage of selection transistors, which can result in malfunction and reduced reliability due to the simultaneous performance of read and precharge operations.
Innovation Solution
A semiconductor device with a fuse array section, control signal generation section, bit line control section, and word line control section that allows for controlled activation of program and read word lines after a predetermined time from the precharge operation, enabling separate and optimized precharge and read operations to manage the drain-source voltage effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If read operation and precharge operation are performed simultaneously, then operational speed is improved, but drain-source voltage increases causing transistor malfunction and reduced reliability
Solution Approach 1:
The patent segments the control of word lines by introducing separate control mechanisms for program word lines and read word lines. The read word line control is divided into precharge phase and read phase, with independent timing control to prevent simultaneous activation that causes voltage conflicts. This segmentation allows the system to maintain both fast operation and transistor reliability.
Solution Approach 2:
The patent implements preliminary action by performing the precharge operation on read word lines before activating the read operation. The control circuit generates a precharge signal that activates read word lines in advance to establish proper voltage levels, then subsequently activates program word lines for the actual read operation. This sequencing prevents voltage conflicts while maintaining operational speed.
2Reliability
If separate control of program and read word lines is implemented, then transistor reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a control circuit that handles both program and read operations through a unified architecture. The same control circuit generates different control signals (program word line control and read word line control) based on the operation type, rather than using completely separate control circuits. This multi-functional approach maintains transistor reliability while minimizing the increase in device complexity.
Solution Approach 2:
The patent introduces an intermediary control mechanism that mediates between the program operation and read operation. The control circuit includes intermediate signals (such as precharge signals and timing control signals) that coordinate the activation of different word lines. This intermediary layer simplifies the overall control logic by providing a structured way to manage the timing and sequencing of multiple word line activations.
Data Source
AI summary
A semiconductor device includes a fuse array section suitable for performing program and read operations; a control signal generation section suitable for generating a precharge control signal and a word line control signal; a bit line control section suitable for controlling a precharge operation of a bit line in response to the precharge control signal and a source signal; and a word line control section suitable for controlling activation of a program word line and a read word line for performing the program and read operations in response to the word line control signal, wherein the control signal generation section controls the word line control signal to be activated after a predetermined time from the activation of the precharge control signal.