Semiconductor Fuse Array Programming for Integration Density
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Solution Overview
Problem
As semiconductor devices become more integrated, the number of failed memory cells increases, limiting the integration density and making it difficult to program fuses within encapsulated semiconductor packages, which hinders the ability to store information for internal control operations effectively.
Innovation Solution
A semiconductor device with a program controller, latch units, and selectors that test memory cells in cell array blocks and selectively program a fuse array based on pass/fail information, allowing addresses of abnormal memory cells to be stored in the fuse array for redundancy purposes, thereby improving integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells is increased to improve integration density, then the integration density is improved, but the number of failed memory cells increases
Solution Approach 1:
The patent divides the memory device into multiple cell array blocks (first cell array block, second cell array block, etc.) with separate test circuits for each block. This segmentation allows independent testing and address latching for each block, enabling systematic management of failed cells across the entire device while maintaining high integration density.
Solution Approach 2:
The patent uses a program controller to change the state of fuse arrays based on test results. When failed memory cells are detected, the controller programs the corresponding fuse arrays to alter their electrical characteristics (from conductive to non-conductive or vice versa), thereby changing the parameter state to mark and compensate for failed cells.
2Ease of manufacture
If general fuses are used to store information, then programming can be done at wafer level, but programming becomes impossible after encapsulation
Solution Approach 1:
The patent introduces e-fuses (electrical fuses) as an intermediary solution between traditional fuses and the need for post-encapsulation programming. These e-fuses are implemented using transistors with controllable resistance states, allowing them to be programmed electrically after the device is encapsulated, thus bridging the gap between manufacturing convenience and operational flexibility.
Solution Approach 2:
The patent replaces traditional mechanical/electrical fuse structures with transistor-based e-fuses that can be controlled through electrical signals. This substitution enables programming operations to be performed remotely after encapsulation by applying voltage signals that change the transistor's resistance state, eliminating the need for physical access to the fuse structures.
3Measurement precision
If transistor size is increased or amplifiers are added to correctly recognize data in e-fuses, then data recognition accuracy is improved, but integration density decreases
Solution Approach 1:
The patent merges multiple fuse arrays into shared groups that can be controlled by common control signals. The program controller manages multiple fuse arrays (first fuse array, second fuse array, etc.) using coordinated selection signals, allowing the system to achieve accurate data recognition through collective control while maintaining high integration density by eliminating redundant individual control circuitry.
4Quantity of substance
If e-fuse arrays are used to improve integration density, then integration density is improved, but multiple e-fuse arrays need to share amplifiers
Solution Approach 1:
The patent implements dynamic control of fuse array selection through time-multiplexed operation. The program controller generates selection signals that dynamically switch which fuse array is active at any given moment, allowing a single amplifier to serve multiple fuse arrays sequentially. This dynamic approach reduces the total number of amplifiers needed while maintaining the ability to program and read all fuse arrays effectively.
Data Source
AI summary
A semiconductor device including a first latch unit suitable for storing a first address of a first memory cell tested in a first cell array block, a second latch unit suitable for storing a second address of a second memory cell tested in a second cell array block, a first selector suitable for receiving a first selection signal or a second selection signal to output any one of the first address and the second address as a selected address, and a program controller suitable for determining whether the selected address has to be stored in a fuse array and to control an operation for programming the fuse array.


