Semiconductor Fuse Element Dielectric Layer Thickness Control

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Solution Overview

Problem

Controlling the thickness and uniformity of the interlayer dielectric layer over fuse elements in semiconductor devices is challenging, leading to issues such as incomplete blowing of fuse elements during laser trimming and potential corrosion, which affects the reliability of semiconductor devices.

Innovation Solution

A method involving multiple etching processes to form a laser access window, including forming a first interlayer dielectric layer, an etching stop layer, and a second interlayer dielectric layer with a planar top surface, followed by selective etching to expose the fuse element and bond pad, ensuring the interlayer dielectric layer thickness is controlled within a specific range to prevent corrosion and ensure proper laser trimming.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a single interlayer dielectric layer is formed over the fuse element, then the formation process is simple, but the thickness and uniformity of the dielectric layer cannot be precisely controlled, leading to incomplete blowing during laser trimming or corrosion of the fuse element

Engineering Contradiction:
Improvesimplicity of dielectric layer formationVSAvoidthickness and uniformity control of interlayer dielectric layer
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The single interlayer dielectric layer is segmented into multiple layers: a first interlayer dielectric layer (ILD1) and a second interlayer dielectric layer (ILD2), separated by an etching stop layer (ESL). This segmentation allows independent control of each layer's thickness, enabling precise control of the total dielectric thickness over the fuse element while maintaining manufacturing simplicity through standardized deposition processes for each layer

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An etching stop layer (ESL) is introduced as an intermediary layer between the first and second interlayer dielectric layers. This mediator layer provides a controlled etching barrier that prevents over-etching during laser access window formation, ensuring that the etching process stops at the desired depth and preserves the precise thickness control of the dielectric structure

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the interlayer dielectric layer thickness is increased to protect the fuse element, then corrosion protection is improved, but the fuse element cannot be properly blown up during laser trimming process

Engineering Contradiction:
Improveprotection of fuse element from corrosionVSAvoidsuccess rate of laser trimming process
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The dielectric structure is segmented into two layers with different thicknesses: a thicker first interlayer dielectric layer (ILD1) that provides corrosion protection, and a thinner second interlayer dielectric layer (ILD2) that allows laser penetration. This segmentation enables the structure to simultaneously provide both protection and laser accessibility

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the dielectric structure have different thicknesses tailored to their specific functions: the first interlayer dielectric layer (ILD1) has greater thickness for corrosion protection in regions where protection is needed, while the second interlayer dielectric layer (ILD2) has reduced thickness in the laser access window region to allow proper laser trimming while maintaining overall structural integrity

Inventive Principle:
Principle #3Local quality

3Productivity

If the interlayer dielectric layer thickness is reduced to enable laser trimming, then laser access is improved, but the fuse element becomes vulnerable to corrosion and damage

Engineering Contradiction:
Improvesuccess rate of laser trimming processVSAvoidprotection of fuse element from corrosion
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The dielectric protection is segmented into two functional layers: the first interlayer dielectric layer (ILD1) provides thick corrosion protection, while the second interlayer dielectric layer (ILD2) provides thin protection that allows laser access. This segmentation enables simultaneous achievement of both protection and laser accessibility

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dielectric structure implements local quality variations where the first interlayer dielectric layer (ILD1) maintains greater thickness for corrosion protection across the fuse element, while the second interlayer dielectric layer (ILD2) has reduced thickness specifically in the laser access window region, providing just enough protection while enabling successful laser trimming

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method achieves improved film thickness and uniformity of the interlayer dielectric layer, enhancing the reliability and yield of semiconductor devices with fuse elements by ensuring precise exposure for laser trimming and preventing corrosion.

Implementation Method 1

A first etching process is performed to pattern the passivation layer, respectively forming a first opening in the first device region and a second opening in the second device region

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

prior to blowing up of the fuse element by methods such as a laser trimming process

Methodology Applied
Scientific EffectLaser ablation: Laser Ablation

Data Source

PatentUS7745343B1Method for fabricating semiconductor device with fuse element
Publication Date: 2010.06.29 VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
  • US7745343B1 patent drawing
  • US7745343B1 patent drawing
  • US7745343B1 patent drawing

AI summary

A method for fabricating a semiconductor device with a fuse element includes providing a semiconductor structure with a fuse element formed over a first device region thereof. A first interlayer dielectric layer, an etching stop layer and a second interlayer dielectric layer are sequentially formed. A bond pad is formed over the second interlayer dielectric layer in a second device region of the semiconductor structure. A passivation layer is formed over the bond pad and the second interlayer dielectric layer. A first etching process is performed to form a first opening in the first device region and a second opening in the second device region, wherein the first opening exposes a portion of the second interlayer dielectric layer over the fuse element and, and the second opening partially exposes a portion of the bond pad. A second etching process and a third etching process are performed to leave another passivation layer conformably covering the fuse element and the semiconductor structure adjacent thereto.