Semiconductor Fuse Formation Using Etch Stop Layers
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Solution Overview
Problem
Conventional semiconductor manufacturing processes face challenges in accurately forming fuses, leading to issues such as under-exposure or breakage during the laser-repair process, due to difficulties in uniformly etching insulation interlayers without an etch stop layer.
Innovation Solution
The introduction of a semiconductor device design that includes a first etch stop layer with etch selectivity, allowing for uniform etching of insulation interlayers and precise formation of fuses, reducing the risk of fuse breakage by using a second etch stop layer and a passivation layer of silicon nitride to protect adjacent fuses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching methods are used without an etch stop layer, then the etching process is simpler, but the insulation interlayers cannot be uniformly etched leading to under-exposure or breakage of fuses
Solution Approach 1:
The patent divides the etching process into multiple stages by introducing etch stop layers at different depths. The first etch stop layer is etched to a first depth, and the second etch stop layer is etched to a second depth, allowing controlled, uniform removal of insulation interlayers without causing fuse breakage or under-exposure.
Solution Approach 2:
The etch stop layers are formed in advance before the final fuse formation process. This preliminary structuring enables precise control during subsequent etching operations, ensuring that insulation interlayers are removed uniformly without damaging the fuses.
2Manufacturing precision
If the first metal layer is etched deeply to expose fuses, then the fuses become accessible for laser repair, but the fuse breaks due to excessive etching
Solution Approach 1:
The etch stop layers are formed in advance at predetermined depths to serve as depth references during etching. This preliminary structuring prevents over-etching that would damage the fuse, while still achieving sufficient exposure for laser repair operations.
Solution Approach 2:
The etch stop layers act as intermediary structures that mediate between the need to expose the fuse for repair and the need to preserve fuse integrity. By controlling etching depth relative to these intermediary layers, precise exposure is achieved without excessive etching.
3Manufacturing precision
If insulation interlayers are over-etched to ensure fuse exposure, then the fuse is fully exposed, but adjacent fuses are damaged
Solution Approach 1:
The patent segments the etching depth control into multiple discrete levels defined by the first and second etch stop layers. This segmentation allows precise control of etching depth, ensuring complete exposure of the target fuse while preventing damage to adjacent fuses through controlled, uniform etching.
Solution Approach 2:
The etch stop layers serve as intermediary reference structures that enable controlled etching. By using these intermediaries, the etching process achieves complete fuse exposure while automatically limiting the etching depth to prevent damage to adjacent fuses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables more uniform formation of fuses, reducing the probability of breakage and ensuring accurate exposure during the laser-repair process, while maintaining the integrity of adjacent fuses.
Implementation Method 1
a first etch stop layer with etch selectivity, allowing for uniform etching of insulation interlayers
Implementation Method 2
ensuring accurate exposure during the laser-repair process
Data Source
AI summary
Semiconductor devices having a plurality of fuses and methods of forming the same are provided. The semiconductor device having a fuse including a substrate having a cell region and/or a fuse box region. A first insulation interlayer may be formed on the substrate. A first etch stop layer may be formed on the first insulation interlayer. A metal wiring including a barrier layer, a metal layer and/or a capping layer may be formed on the first etch stop layer of the cell region. Fuses, spaced apart from each other, may be formed on the first etch stop layer of the fuse box region. Each fuse may include the barrier layer and/or the metal layer. A second insulation interlayer having an opening exposing the fuse box region may be formed on the metal wiring and/or the first etch stop layer. The etch stop layer may allow the fuses to be formed more uniformly and decrease the probability of breaking the fuses.