Semiconductor Gap Filling via Epitaxial Growth and Selective Etching
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Solution Overview
Problem
The existing methods for filling gaps in semiconductor devices with silicon often result in non-uniform growth, leading to voids due to differential deposition rates and incomplete nucleation on side and bottom surfaces.
Innovation Solution
A method involving a semiconductor substrate with a crystalline bottom and amorphous side walls, where a silicon precursor is deposited to promote epitaxial growth on the bottom and an etchant is used to selectively etch the amorphous silicon deposition on the side walls, allowing for uniform filling of the gap without creating voids.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If silicon is deposited to fill the gap from the sides and bottom, then the gap filling is achieved, but non-uniform growth causes voids to form in the interior
Solution Approach 1:
The patent applies local quality by creating different surface conditions at different locations within the gap. The bottom surface is prepared with a crystalline seed layer that promotes ordered epitaxial growth, while the side walls retain their amorphous nature which is selectively etched. This local differentiation ensures uniform silicon deposition from the bottom upward without void formation, as the crystalline structure guides consistent layer-by-layer growth throughout the gap volume.
Solution Approach 2:
The patent employs preliminary action by preparing the bottom surface with a crystalline seed layer before initiating silicon deposition. This pre-preparation step creates a nucleation template that directs uniform epitaxial growth from the outset. Additionally, the side walls are pre-treated with an amorphous layer that will be selectively etched, establishing the conditions for uniform filling before the actual silicon deposition begins.
2Productivity
If deposition rate is increased to improve productivity, then filling speed increases, but voids form due to differential deposition rates
Solution Approach 1:
The patent applies parameter changes by controlling the deposition conditions to favor epitaxial growth on the crystalline bottom surface. By adjusting deposition parameters such as temperature, pressure, and precursor flow rates, the process enables high-speed filling while maintaining uniformity. The crystalline seed layer acts as a template that guides uniform deposition even at higher rates, preventing the differential deposition that would otherwise create voids.
3Reliability
If amorphous material is present on side walls, then nucleation is inhibited, but incomplete nucleation causes voids on the bottom or side
Solution Approach 1:
The patent applies local quality by creating distinct material phases at different locations: a crystalline seed layer on the bottom surface and an amorphous layer on the side walls. The crystalline bottom provides a template for complete and uniform nucleation, while the amorphous side walls are selectively etched to prevent unwanted nucleation. This spatial differentiation ensures complete nucleation on the bottom without void formation, while controlling side wall interactions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the uniform filling of gaps with silicon, providing an effective electrical contact between layers by controlling the deposition and etching processes to prevent void formation, thereby enhancing the quality of semiconductor devices.
Implementation Method 1
A silicon precursor is deposited in the gap to cause an epitaxial growth of the crystalline semiconducting material on the bottom of the gap
Implementation Method 2
an etchant is provided in the gap to etch an amorphous deposition of the silicon precursor on the side walls of the gap
Data Source
AI summary
Method for filling a gap, comprisingproviding in a deposition chamber a semiconductor substrate having a gap, wherein a bottom of the gap includes a crystalline semiconducting material and wherein a side wall of the gap includes an amorphous material;depositing a silicon precursor in the gap.