Semiconductor Package Structure With Gap Filling for Heat and Stress Relief
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Solution Overview
Problem
Current Chip-On-Wafer-On-Substrate (CoWoS) packaging technology faces challenges in efficiently managing heat dissipation and stress distribution across semiconductor packages, leading to potential warpage and delamination issues.
Innovation Solution
The implementation of a package structure that includes multiple semiconductor packages bonded to a substrate with an underfill material filling the gaps between packages, a gap filling structure to connect packages, and a heat dissipation structure attached via a thermal conductive layer, which helps in reducing stress and improving thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple semiconductor packages are bonded closely to a substrate to improve integration density, then the area utilization is improved, but heat dissipation becomes insufficient and stress distribution deteriorates
Solution Approach 1:
A gap filling structure is introduced as an intermediary element between adjacent semiconductor packages. This gap filling structure serves as a thermal pathway that conducts heat away from the packages, while also acting as a stress distribution medium that prevents warpage and delamination, thus resolving the contradiction between close packaging and heat dissipation.
2Area of stationary object
If semiconductor packages are bonded closely to improve integration density, then area utilization is improved, but stress distribution deteriorates leading to warpage
Solution Approach 1:
The gap filling structure acts as a stress-distributing intermediary between packages and the substrate. It provides mechanical support and stress relief, preventing warpage and delamination that would otherwise occur due to thermal expansion and contraction stresses in closely packed packages.
3Device complexity
If conventional packaging is used without gap filling structures, then device complexity is reduced, but delamination occurs due to poor stress management
Solution Approach 1:
The gap filling structure serves as a protective intermediary layer that prevents delamination by distributing thermal and mechanical stresses uniformly across the package-substrate interface, thereby improving reliability without requiring complex multi-layer structures.
Solution Approach 2:
The gap filling structure modifies the thermal and mechanical parameters of the package assembly by providing a material with intermediate properties between the semiconductor packages and the substrate, thereby changing the stress distribution pattern and preventing delamination.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances thermal dissipation performance, reduces warpage, and prevents delamination, thereby improving the reliability and efficiency of the package structure.
Implementation Method 1
a heat dissipation structure attached via a thermal conductive layer, which helps in reducing stress and improving thermal dissipation
Data Source
AI summary
A package structure includes a package substrate, a first semiconductor package and a second semiconductor package, an underfill material, a gap filling structure and a heat dissipation structure. The first semiconductor package and the second semiconductor package are electrically bonded to the package substrate. The underfill material is disposed to fill a first space between the first semiconductor package and the package substrate and a second space between the second semiconductor package and the package substrate. The gap filling structure is disposed over the package substrate and in a first gap laterally between the first semiconductor package and the second semiconductor package. The heat dissipation structure is disposed on the package substrate and attached to the first semiconductor package and the second semiconductor package through a thermal conductive layer.