Semiconductor Package Gap-Fill Bonding for Void-Free Thick Die Stacks

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Solution Overview

Problem

In the manufacturing of multi-chip semiconductor packages, the thick top core die poses challenges in bonding, leading to void formation and compromised bonding quality due to its rigidity, which hinders effective deformation during the die-to-wafer bonding process.

Innovation Solution

A semiconductor package design incorporating a buffer die with an intermediate core die stack and a top core die stack, where the gap filling portions, acting as flexibility compensating layers, are directly bonded to each other, preventing voids at the bonding interface by allowing for deformation during wafer-to-wafer bonding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Strength

If the top core die has a relatively large thickness to maintain structural integrity, then the structural strength is improved, but the ability to deform during bonding is worsened, resulting in void formation at the bonding interface

Engineering Contradiction:
Improvestructural integrityVSAvoidbonding quality
Core Design Contradiction:
StrengthVSManufacturing precision

Solution Approach 1:

The top core die is divided into two separate components: a thick core die providing structural integrity and a thin flexibility compensating layer enabling deformation during bonding. This segmentation allows each component to fulfill its specific function - the core die maintains strength while the flexibility layer ensures void-free bonding by deforming during the bonding process

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the top core die structure are given different properties. The core die region has large thickness for structural integrity, while the flexibility compensating layer has small thickness for deformability. This local differentiation of quality allows the system to simultaneously achieve both structural strength and bonding quality

Inventive Principle:
Principle #3Local quality

2Strength

If the top core die is made thick to maintain structural integrity, then the strength is improved, but the deformation capability during bonding is reduced, leading to voids at the bonding interface

Engineering Contradiction:
Improvestructural integrityVSAvoiddeformation capability
Core Design Contradiction:
StrengthVSAdaptability or versatility

Solution Approach 1:

The top core die is segmented into a structural core component and a flexible compensating layer. The core die maintains thickness for structural integrity while the flexibility compensating layer provides the necessary deformation capability during bonding through its thin structure and material properties

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The top core die structure uses a composite configuration combining a thick core die (providing structural integrity) with a thin flexibility compensating layer (providing deformation capability). This composite structure integrates materials or layers with different mechanical properties to simultaneously achieve strength and adaptability

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances bonding quality by ensuring void-free interfaces and improved structural integrity in multi-chip semiconductor packages, particularly for thick top core dies, by allowing for flexibility and effective bonding through hybrid bonding techniques.

Implementation Method 1

improved bonding quality by ensuring void-free interfaces and improved structural integrity in multi-chip semiconductor packages, particularly for thick top core dies, by allowing for flexibility and effective bonding through hybrid bonding techniques

Methodology Applied
Scientific EffectHybrid bonding: Diffusion Welding

Data Source

PatentUS20240421130A1Semiconductor package and method of manufacturing the semiconductor package
Publication Date: 2024.12.19 SAMSUNG ELECTRONICS CO LTD
  • US20240421130A1 patent drawing
  • US20240421130A1 patent drawing
  • US20240421130A1 patent drawing

AI summary

A semiconductor package includes a buffer die, an intermediate core die stack stacked on the buffer die, the intermediate core die stack including a plurality of intermediate core dies and a first gap filling portion covering outer surfaces of the plurality of intermediate core dies, and a top core die stack stacked on the intermediate core die stack, the top core die stack including a top core die and a second gap filling portion covering an outer surface of the top core die. The first gap filling portion and the second gap filling portion are directly bonded to each other.