Semiconductor Gate Air Spacers for Lower Parasitic Capacitance
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Solution Overview
Problem
Conventional methods of semiconductor fabrication are unable to reliably form air spacers, which are necessary to reduce parasitic capacitance and improve device performance in modern FET devices.
Innovation Solution
A sacrificial layer, such as amorphous silicon or silicon germanium, is used to form air spacers by etching selectivity, followed by a sealing layer to trap air gaps, creating low dielectric constant spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication methods are used, then manufacturing process simplicity is maintained, but air spacers cannot be reliably formed
Solution Approach 1:
A sacrificial layer is formed in advance before the final air spacer structure is needed. This preliminary layer serves as a template that guides subsequent processing steps, ensuring reliable air spacer formation without requiring complex direct fabrication methods.
Solution Approach 2:
The sacrificial layer acts as an intermediary material that enables air spacer formation. It is temporarily introduced into the structure, performs its guiding function, and is then removed to leave the desired air spacer configuration, simplifying the overall process while improving reliability.
2Object-affected harmful factors
If air spacers are formed to reduce parasitic capacitance, then device performance is improved, but fabrication complexity increases
Solution Approach 1:
The harmful parasitic capacitance is addressed by extracting or removing material to create air gaps. The sacrificial layer removal process effectively 'takes out' the unwanted capacitance-forming material, leaving air spacers that minimize parasitic effects without requiring complex alternative structures.
Solution Approach 2:
The dielectric constant parameter is changed by replacing solid dielectric material with air (which has a near-unity dielectric constant). This parameter change directly reduces parasitic capacitance, and the sacrificial layer method provides a straightforward pathway to achieve this change without complex processing.
3Productivity
If device geometry is scaled down, then production efficiency is increased, but parasitic capacitance increases
Solution Approach 1:
Instead of uniformly scaling all dimensions, the invention applies local quality changes by introducing air spacers in specific critical regions where parasitic capacitance has the greatest impact. This localized approach addresses the harmful effect without requiring further reduction of overall device geometry, maintaining production efficiency.
Solution Approach 2:
The structure transitions from homogeneous dielectric materials to a composite structure incorporating air gaps alongside solid dielectric regions. This composite approach allows optimization of electrical properties (reducing parasitic capacitance) while maintaining the mechanical and manufacturing advantages of scaled-down geometries.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance, enhancing device speed and performance by using air spacers with controlled size and shape.
Implementation Method 1
A sacrificial layer, such as amorphous silicon or silicon germanium, is used to form air spacers by etching selectivity
Implementation Method 2
followed by a sealing layer to trap air gaps, creating low dielectric constant spacers
Data Source
AI summary
A dummy gate is formed over a substrate. A sacrificial layer is formed over the dummy gate. An interlayer dielectric (ILD) is formed over the dummy gate and over the sacrificial layer. The dummy gate is replaced with a metal-containing gate. The sacrificial layer is removed. A removal of the sacrificial layer leaves air gaps around the metal-containing gate. The air gaps are then sealed.