Nonvolatile Semiconductor Gate Structure Aspect Ratio Reduction
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Solution Overview
Problem
Conventional non-volatile memory devices face issues with high aspect ratio gate structures leading to mechanical stress, bowing, electrical bridging, and signal delay due to high resistance control gates, which affect device reliability and operating speed.
Innovation Solution
A floating gate structure with a multiple-layered control gate comprising a lower polysilicon layer, an intermediate barrier layer, and a thin upper metal layer is used, along with a method that forms the upper conductive layer after gate patterning to prevent oxidation and allow for effective polymer removal, reducing the aspect ratio and improving adhesion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a thick silicide layer is used for the control gate, then adhesion is improved, but the aspect ratio increases and resistance increases
Solution Approach 1:
The patent changes the material parameter from silicide to metal (such as tungsten), which allows achieving the required adhesion strength with a much thinner layer thickness, thereby reducing the aspect ratio from 6.4 to 3.1 while maintaining or improving adhesion properties
Solution Approach 2:
The control gate is formed as a composite structure combining a polysilicon layer and a metal layer, where each material contributes its advantageous properties: polysilicon provides good adhesion to the underlying layers, while the metal layer provides low resistance and reduced aspect ratio
2Strength
If a multiple-layered control gate with silicide is used, then adhesion is improved, but resistance increases causing signal delay
Solution Approach 1:
The control gate combines polysilicon and metal layers, where the metal layer (such as tungsten) provides low electrical resistance for fast signal transmission, while the polysilicon layer ensures good adhesion to the underlying tunneling oxide and floating gate structures
Solution Approach 2:
The patent changes the upper layer material from high-resistance silicide to low-resistance metal, dramatically reducing the electrical resistance of the control gate and eliminating signal delay issues while maintaining adhesion through the polysilicon-metad interface
3Object-affected harmful factors
If post-oxidation is performed to mitigate etch damage, then sidewall protection is improved, but metal layer oxidation occurs causing delamination
Solution Approach 1:
The patent performs the oxidation process before depositing the metal layer, so that the polysilicon sidewalls are protected with oxide before metal deposition. This preliminary oxidation protects the polysilicon from etch damage during subsequent processing steps without exposing the metal layer to oxidation that would cause delamination
Solution Approach 2:
Instead of oxidizing after metal deposition (which causes metal oxidation and delamination), the patent inverts the sequence by oxidizing the polysilicon sidewalls before metal layer formation, thereby protecting the polysilicon without exposing the metal to harmful oxidation
4Object-generated harmful factors
If strong wet etch solvent is used to remove polymers, then polymer removal is improved, but metal layer damage occurs
Solution Approach 1:
The patent performs polymer removal before metal layer deposition, when the structure is more accessible and less sensitive to etch damage. This preliminary cleaning eliminates polymer particles that would cause electrical bridging, without exposing the sensitive metal layer to strong wet etch solvents
Solution Approach 2:
Instead of removing polymers after metal deposition (which risks metal layer damage), the patent inverts the sequence by removing polymers before metal layer formation, thereby ensuring complete polymer removal while protecting the metal layer from etch damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the likelihood of gate bowing and electrical bridging, maintains low resistance, and ensures reliable polymer removal, enhancing device reliability and operating speed by avoiding oxidation of the upper conductive layer and allowing for thicker, lower resistance word lines.
Implementation Method 1
The intermediate barrier layer further improves adhesion between the upper metal layer and lower polysilicon layer, while at the same time, preventing the silicon atoms of the lower polysilicon layer from reacting with the metal atoms of the metal layer
Implementation Method 2
a post-oxidation process is performed following etch of the gate patterns, in an effort to mitigate etch damage to sidewalls of the lower polysilicon layer of the control gate
Implementation Method 3
as a result of the post-oxidation process, the sidewalls of the metal layer also become oxidized, which can lead to an increase in the resistance of the metal layer, and which can cause delamination between the metal layer and the underlying barrier layer
Data Source
AI summary
In a method for manufacturing a semiconductor device, an oxide layer, a first polysilicon layer, and a second polysilicon layer are sequentially provided on a substrate. A first hard mask pattern is provided on the second polysilicon layer. The oxide layer, the first polysilicon layer, and the second polysilicon layer are patterned using the first hard mask pattern as a mask to form a lower gate structure including an oxide pattern, a first polysilicon pattern, and a second polysilicon pattern. The lower gate structure is etched to provide an oxidation layer on sidewalls of the lower gate structure. An insulating layer is provided on the lower gate structure including the oxidation layer. The first hard mask pattern is removed to form a first opening in the insulating layer, the first opening exposing the second polysilicon pattern. A metal pattern is formed in the first opening on the second polysilicon pattern, the second polysilicon pattern having the oxidation layer on sidewalls thereof.